Patents Examined by T. M. Arroyo
  • Patent number: 6087727
    Abstract: An object is to provide a structure of a semiconductor device which allows higher degree of integration both in vertical and horizontal directions, and to provide manufacturing method therefor. The semiconductor device includes source.drain electrodes connected to n.sup.- and n.sup.+ source.drain regions of an MISFET and has a function as a part of a bit line, and a gate electrode connected to a first interconnection as a word line. Electrodes are insulated from each other by a sidewall insulating film, silicon oxide film or a silicon nitride film provided inbetween. Since the word line and the bit line do not cross in the same plane, the difference in level in the vertical direction can be reduced.
    Type: Grant
    Filed: July 15, 1996
    Date of Patent: July 11, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiaki Tsutsumi
  • Patent number: 5834849
    Abstract: An integrated circuit with high density pad structures is provided. The circuit has circuitry covered by an insulating layer. Pads are formed on the insulating layer overlapping the circuitry. A pattern of holes in the insulating layer allows electrical connections to be formed between the pads and the underlying circuitry. Because the pads are formed on top of the circuitry, the die area occupied by pads is reduced relative to the die area occupied by circuitry. The pads are suitable for flip-chip bonding to a package such as a multichip module or conventional wire bonding.
    Type: Grant
    Filed: February 13, 1996
    Date of Patent: November 10, 1998
    Assignee: Altera Corporation
    Inventor: Christopher F. Lane
  • Patent number: 5831337
    Abstract: A vertical transistor is provided on and extends in a first direction along a surface of a substrate. A bump electrode is formed over the transistor and crosses the transistor in a second direction perpendicular to the first direction. The bump electrode is butterfly-shaped and has a first area overlapping the transistor and a second area that does not overlap with the transistor. The size of the second area in the first direction is greater than the size of the first area in the first direction. The bump electrode shape has no interior angle exceeding 270.degree..
    Type: Grant
    Filed: July 26, 1996
    Date of Patent: November 3, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroya Sato
  • Patent number: 5821563
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device comprising an insulated gate field effect transistor provided with a region having added thereto an element at least one selected from the group consisting of carbon, nitrogen, and oxygen, said region having established at either or both of the vicinity of the boundary between the drain and the semiconductor layer under the gate electrode and the vicinity of the boundary between the source and the semiconductor layer under the gate electrode for example by ion implantation using a mask. It is free from the problems of reverse leakage between the source and the drain, and of throw leakage which occurs even at a voltage below the threshold ascribed to the low voltage resistance between the source and the drain.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: October 13, 1998
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 5814841
    Abstract: A self scanning light-emitting array is disclosed. A coupled array of light-emitting elements is constituted so that a light-emitting element in a minimal conducting state influences the next light-emitting element so that its threshold level is changed. When each element is driven by a common clock pulse, the change in threshold level is shifted in the longitudinal direction, so that a minimal conducting state is transferred in a clock period of the clock pulse.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: September 29, 1998
    Assignee: Nippon Sheet Glass Co., Ltd.
    Inventors: Yukihisa Kusuda, Kiyoshi Tone, Ken Yamashita, Shuhei Tanaka
  • Patent number: 5814888
    Abstract: A semiconductor device with a multilayer wiring structure has an insulating substrate and first conductors formed on top of the insulating substrate with a groove between neighboring first conductors. An insulating film covers the first conductors as well as the grooves between the neighboring first conductors. A void serving to reduce electrostatic capacitance between the conductors is formed in the grooves. An interlayer insulating film is formed on top of the first conductors to prevent leakage current, and second conductors are formed on top of the interlayer insulating film.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: September 29, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Yasushiro Nishioka, Tsuyoshi Tanaka, Kyung-ho Park, Yasutoshi Okuno
  • Patent number: 5793113
    Abstract: The present invention provides a novel interconnection structure which comprises an insulation layer having a contact hole which extends in a first vertical direction, a contact layer residing within the contact hole and being made of a first conductive material which has a first electromigration resistance, and an interconnection layer extending within the insulation layer. The interconnection layer has one end portion which is in contact with one end of the contact layer. The interconnection layer is made of a second conductive material having a second electromigration resistance which is smaller than the first electromigration resistance. The interconnection layer has a reservoir portion which is made of the second conductive material. The reservoir portion extends within the insulation layer and extends from the one end portion of the interconnection layer in a second vertical direction which is opposite to the first vertical direction.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: August 11, 1998
    Assignee: NEC Corporation
    Inventor: Noriaki Oda
  • Patent number: 5783860
    Abstract: A method of bonding an integrated circuit die to a heat sink by first providing a lead frame that has a die paddle portion having a top surface, a bottom surface, and at least one aperture therethrough, positioning a heat sink abutting the bottom surface of the die paddle portion, and then pressing an integrated circuit die against the top surface of the die paddle portion with an adhesive material sandwiched therein between such that the adhesive flows through at least one aperture in the die paddle portion to bond the integrated circuit die and the heat sink together.
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: July 21, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Jian Dih Jeng, Hsing Seng Wang
  • Patent number: 5780926
    Abstract: A multichip package device includes a lead frame having supporting portions and lead portions for electrically connecting the multichip package with an external electronic device. The multichip package is formed by depositing first and second inner insulation layers on lower and upper surfaces of the lead frame, respectively. Via holes are then formed through the first and the second inner insulation layers. First and second metallization layers are deposited and patterned on lower and upper surfaces of the first and the second inner insulation layers, respectively. First and second outer insulation layers are then deposited on lower and upper surfaces of the first and the second patterned metallization layers, respectively. A plurality of chips, each having an active surface on which a plurality of bonding pads are formed, are attached to lower and upper surfaces of the first and second outer insulation layers.
    Type: Grant
    Filed: February 14, 1997
    Date of Patent: July 14, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jeong Woo Seo
  • Patent number: 5780928
    Abstract: An electronic system having improved thermal transfer from a semiconductor die in a semiconductor device assembly (package) by at least partially filling a cavity in the package with a thermally conductive fluid, immersing a heat collecting portion of a heat pipe assembly into the fluid, and sealing the cavity. In order that the thermally conductive fluid does not chemically attack the die or its electrical connections, the die and connections can be completely covered with an encapsulating coating of an inorganic dielectric material, such as silicon dioxide, by any of a variety of techniques. The heat pipe provides highly efficient heat transfer from within the package to an external heat sink by means of an evaporation-condensation cooling cycle. The optional dielectric coating over the die permits selection of the thermally conductive fluid from a wider range of fluids by isolating the die and its electrical connections from direct contact with the fluid.
    Type: Grant
    Filed: April 9, 1996
    Date of Patent: July 14, 1998
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Mark R. Schneider, Nicholas F. Pasch
  • Patent number: 5777345
    Abstract: An electronic package which has a plurality of stacked integrated circuit dies. The package includes a first die that is mounted to a die paddle of a lead frame. The first die is also connected to the leads of the lead frame by bond wires. A second die is mounted to the top surface of the first die and electrically connected to the first die with bond wires. The first die, second die and die paddle are all enclosed by a package.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: July 7, 1998
    Assignee: Intel Corporation
    Inventors: William G. Loder, John Francis McMahon
  • Patent number: 5773878
    Abstract: The present invention relates to a lead frame design for IC packaging to reduce chip stress and deformation and to improve mold filling. The die-pad is split into several sections which are jointed together by flexible expansion joints. The split die-pad allows relative motion between the pad and the chip during die attach cure. It also breaks down the total die pad area (and length) that is rigidly attached to the chip into smaller sections. These two factors reduce the magnitude of coefficient-of-thermal expansion (CTE) mismatch and out of plane deformation of the assembly, resulting in lower chip stress and deformation and improved package moldability.
    Type: Grant
    Filed: January 4, 1996
    Date of Patent: June 30, 1998
    Assignee: Institute of Microelectronics National University of Singapore
    Inventors: Thiam Beng Lim, Sarvotham M. Bhandarkar
  • Patent number: 5773879
    Abstract: The semiconductor package and manufacturing method thereof whereby the inexpensive package of high thermal conductivity is obtained by applying a Cu/Mo/Cu clad material for a base plate which matches the thermal expansion of a semiconductor chip, and the inexpensive package with high heat transfer suitable for a high frequency device is obtained by controlling a thickness of glass, and a size of a lead (width, thickness), thereby to match impedance of a wiring portion with that of the semiconductor chip, by plating only necessary areas with Au, and by plating the exterior with Sn.
    Type: Grant
    Filed: February 9, 1993
    Date of Patent: June 30, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tosihiro Fusayasu, Kenji Kagata, Hirotugu Yamada, Isao Kitamura, Masanobu Kohara, Mitsuyuki Takada
  • Patent number: 5763940
    Abstract: The size reduction on a longer side of a semiconductor apparatus mounted on a TAB mounting package is accomplished by slits 105' that are in contact with left and right edge portions of a potting resin 102 and that are longer than sides in the vertical direction of a base film 104. In addition, the size reduction in the vertical direction is accomplished by a structure of which an edge portion in an output outer lead portion 107 extends to the inside of a mounting region 402 of an IC chip 303 (namely, a portion below the IC chip 303) and this portion is connected to the outside of the semiconductor apparatus.
    Type: Grant
    Filed: May 31, 1995
    Date of Patent: June 9, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuko Shibusawa, Takeshi Sasaki
  • Patent number: 5742100
    Abstract: A flip-chip structure and method connects a semiconductor chip (11) having conductive bumps (16) to a substrate (12) having vias (19) extending from a first side (21) to a second side (18) of the substrate (12). A filler material (22) is deposited into the vias (19), and the conductive bumps (16) are inserted into the vias (19) for connecting the semiconductor chip (11) to a conductive element (17) covering the vias (19) on the second side (18) of the substrate (12).
    Type: Grant
    Filed: March 27, 1995
    Date of Patent: April 21, 1998
    Assignee: Motorola, Inc.
    Inventors: Jack A. Schroeder, Conrad S. Monroe
  • Patent number: 5739586
    Abstract: A heat sink assembly includes a printed wiring board, a metal case and a circuit package containing a gallium arsenide field effect transistor heat dissipating circuit. The circuit package includes a metal slug formed integrally with the circuit package, the heat dissipating circuit being bonded to an obverse surface of the metal slug. The printed wiring board includes first and second metal lands, the first metal land being disposed on an obverse surface of the printed wiring board, the second metal land being disposed on a reverse surface of the printed wiring board. A solder film is formed bonded to and thermally coupling a reverse surface of the metal slug to the first metal land, and a plurality of solder posts are formed, each post bonding to and thermally coupling the first metal land to the second metal land. The metal case is pressed against the second metal land with a grease film of thermally conductive grease squeezed therebetween.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: April 14, 1998
    Assignee: Scientific-Atlanta, Inc.
    Inventors: Sharon M. Cannizzaro, Libbie R. Terwilliger, Timothy B. Tunnell, Wayne P. Vaughn, Steven Veneman
  • Patent number: 5739556
    Abstract: In a pressure contact housing for semiconductor components, the gate electrode contact ring 4 is provided with spiral recesses 5. The latter can absorb axial movements produced during the assembly of the housing, without loading the material. A good and durable electrical contact between the gate electrode and the gate electrode contact ring is obtained thereby.
    Type: Grant
    Filed: February 1, 1996
    Date of Patent: April 14, 1998
    Assignee: Asea Brown Boveri AG
    Inventor: Fabio Bolgiani
  • Patent number: 5731634
    Abstract: The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80.degree. to 500.degree. C.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: March 24, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun-ichi Wada
  • Patent number: 5731602
    Abstract: The present invention provides for an improved package for a laser diode. The package has portions of its inner surfaces covered with a non-reflecting material, such as simple black paint, non-reflective metals or specific anti-reflection coatings. Such non-reflecting materials surprisingly enhances the performance of packaged laser diodes used as pumping lasers for fiber amplifiers, for example.
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: March 24, 1998
    Assignee: E-Tek Dynamics, Inc.
    Inventors: Jing-Jong Pan, Paul Shi-Qi Jiang, Jian Chen, Li-Hua Wang
  • Patent number: 5731633
    Abstract: An improved multichip semiconductor module compatible with existing SIMM memory sockets comprising a molded module frame and a composite semiconductor substrate subassembly received in a cavity in said frame. The composite semiconductor substrate subassembly or subassembly(s) comprises a plurality of semiconductor devices which are connected to electrical contacts on an edge of the molded frame by a variety of configurations described herein. In one embodiment of the invention, the subassembly(s) includes a composite substrate which comprises a thin metal cover plate and thin laminate circuit which is bonded to the metal cover plate by a film adhesive. The composite substrate provides a mounting surface for the placement of semiconductor devices and their associated passive components.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: March 24, 1998
    Assignee: Gary W. Hamilton
    Inventor: James E. Clayton