Abstract: A circuit arrangement and a power semiconductor module are provided in which the circuit arrangement comprises a plurality of parallel-connected power semiconductor modules, of which only one is connected to a control device. The other modules function as slaves of the master connected to the control device and draw the signal required for triggering from the master via a signal bus. For this purpose, the power semiconductor modules have a number of signal connections which are interconnected. The signal connections may be connected signalwise to the gate connections, for example via an interface. The power semiconductor modules according to the invention provide a circuit arrangement in which a plurality of modules can be connected in parallel up to maximum performances without limitations.

Abstract: An electronic package which includes a rigid support member, e.g., copper sheet, to which is bonded both the package's semiconductor chip and circuitized substrate members. The chip is bonded using a thermally conductive adhesive while the circuitized substrate, preferably a flexible circuit, is bonded using an electrically insulative adhesive. The chip is electrically coupled to designated parts of the circuitry of the substrate, preferably by wire, thermocompression or thermosonic bonding. An encapsulant may be used to cover and protect the connections between the chip and substrate. This package may in turn be electrically coupled to a separate, second substrate such as a PCB.

Abstract: An isolating/insulating film is formed on the surface of a p.sup.- silicon substrate in an element isolating region. An nMOS transistor having a pair of n-type source/drain regions is formed within an element forming region isolated by the isolating oxide film. A p.sup.+ impurity diffusion region is formed on the p.sup.- silicon substrate in such a manner as to be contacted with the lower surface of the isolating oxide film in the element isolating region and to extend at a specified depth from the surface of the p.sup.- silicon substrate in the element forming region. A p-type impurity diffusion region having a p-type impurity concentration higher than that of the p.sup.- silicon substrate is formed at the side end portion of the isolating oxide film in such a manner as to be contacted with the n-type source/drain region. With this arrangement, it is possible to reduce leakage current caused by the distribution of crystal defects in a depletion layer.

Abstract: A TiSi.sub.2 /TiN clad LI strap process and structure are disclosed which combine the advantages of both TiSi.sub.2 and TiN LI processes. According to the invention, the retention of a thin TiN layer between the local interconnect and contacts provides a diffusion barrier against counterdoping and relaxes the thermal budget for subsequent processing.

Abstract: An integrated circuit device with a light-emitting diode thereon is disclosed. The device has discrete regions which function in concert to emit light when a suitable amount of voltage is provided. The device has four discrete regions: a first doped silicon region; a second silicon dioxide region; a third organic material region; and a fourth conducting material region. The first and fourth regions are electrodes which inject holes and electrons into the conducting organic material. The second region lowers the energy barrier between the first and third regions which improves the efficiency with which the polymer emits light. The diode of the present invention is fabricated on an integrated circuit using conventional integrated circuit fabrication techniques.

Abstract: The content of bonding hydrogen in an a - SiGe film is so adjusted that in a case where the content of bonding hydrogen per Si atom in the film is in the range of approximately 8 to 14 at. %, [SiH.sub.2 ]/[Si] and [SiH]/[Si] are respectively in the ranges of approximately 0.5 to 4 at. % and approximately 7 to 10 at. %, and both [SiH.sub.2 ]/[Si] and [SiH]/[Si] increase at approximately equal slops as the content of bonding hydrogen increases.

Abstract: An integrated circuit chip stack includes a stack of chip packages mounted on a substrate. Each chip package includes a plastic packaged chip mounted within a central aperture in a thin, planar frame by soldering leads at opposite ends of the plastic package to conductive pads on an upper surface of the frame adjacent the central aperture. Conductive traces and vias couple the conductive pads to other conductive pads on upper and lower surfaces of the frame adjacent outer edges thereof. The conductive pads adjacent the outer edges are soldered to the conductive pads of adjacent chip packages by dipping the edges of an assembled stack of the chip packages in solder. The chip stack thus formed is mounted on a substrate. Each chip package can be individually addressed by the substrate, such as to enable the chip therein, using a stair step arrangement of the conductive pads in which the pads on the opposite surfaces of each frame are coupled in offset fashion by vias extending through the frame.

Abstract: A surface mount electronic device, attachable to a circuit board, comprises an insulating substrate having a top surface and a bottom surface; a plurality of metallized terminal pads on the bottom surface; and a plurality of leads, each attached to one of the terminal pads by a solder column. Each of the leads comprises a first substantially horizontal lead portion attached to one of the terminal pads by the solder column. A plurality of upturned prongs on the first substantially horizontal lead portion forms a pronged area configured to hold the solder column. A second substantially horizontal lead portion terminates in a free end for attachment to the circuit board. An upwardly curved intermediate lead portion connects the first and second substantially horizontal portions and underlies the bottom surface of the substrate.

Abstract: There is provided a molded plastic electronic package having improved thermal dissipation. A thermal dissipator, such as a heat spreader or a heat slug is partially encapsulated in the molding resin. The thermal dissipator has a density less than that of copper and a coefficient of thermal conductivity that is constant or increases as the package periphery is approached.

Abstract: A repair structure for an array with first and second sets of lines that cross includes a repair line extending within the array, approximately parallel to at least one line in the first set and crossing a subset of the lines in the second set. The repair line is separated from the lines it crosses by an insulating layer but a repair operation can form an electrical connection between the repair line and an open line it crosses by operating on the region where they cross. For example, the insulating layer can be melted so that molten metal from the lines mixes to form an electrical connection. The repair structure also includes a connecting lead outside the array through which the repair line can be electrically connected to the signal circuitry for the open line, so that the open line receives signals from or provides signals to its signal circuitry as though it were continuous.

Abstract: In a lead frame for a semiconductor device which includes a multiplicity of leads, and a heat spreader having an edge to which the leads are bonded by an insulating material coated with an adhesive, and a central portion to which a semiconductor chip is bonded, the heat spreader has a ring-shaped portion defined between its central portion and the inner ends of the leads, and having a width of at least 0.5 mm. The ring-shaped portion has a plurality of through holes occupying not more than 60% by area of that portion, and each of those holes has a width of at least 0.5 mm.

Abstract: A semiconductor device is provided with a stack of a plurality of semiconductor elements each having a bump deposited on each of surface electrodes, and a plurality of leads disposed closely adjacent to the stacked semiconductor elements, the leads being bonded to the bumps respectively thereby structurally integrally assembling the plural semiconductor elements.

Abstract: A planarization process for the manufacturing of highly-planar interlayer dielectric thin films in integrated circuits, particularly in non-volatile semiconductor memory devices, comprises the steps of: forming a first barrier layer over a semiconductor substrate wherein integrated devices have been previously obtained; forming a second layer of oxide containing phosphorous and boron over the first undoped oxide the concentration of boron being lower than the concentration of phosphorous; forming a third layer of oxide containing phosphorous and boron over the second oxide layer, the concentration of phosphorous being lower than or equal to the concentration of boron; performing a thermal process at a temperature sufficient to melt the third oxide layer, to obtain a planar surface.

Abstract: A DRAM includes a package, a semiconductor chip housed in the package, and a plurality of leads each disposed from the outside of the package over the periphery of the semiconductor chip. The power supply potential is applied to some of the leads. Corresponding to one power supply lead, one power supply pad and one selection pad are formed. Corresponding to another power supply lead, another power supply pad and another selection pad are formed. Each of these two selection pads is connected or not connected to the corresponding power supply lead by bonding. As a result, one of four word configurations is selected. Since these two selection pads are disposed in the vicinity of the corresponding power supply leads, respectively, the number of times of bonding to one power supply lead is reduced.

Abstract: A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.

Abstract: A heat sink is attached to a semiconductor element functioning as an exothermic element, which is mounted on a circuit board and has a predetermined allowable power consumption, thereby cooling the semiconductor element. A semiconductor element having a lower allowable power consumption than the semiconductor element having the predetermined power consumption, which is hardly exposed to a cooling air flow cooled via the heat sink, is connected to a heat conductive auxiliary member connected at one end to the heat sink. Thus, the heat radiation efficiency of the semiconductor element having the lower allowable power consumption is enhanced.

Abstract: An electronic package which includes a rigid support member, e.g., copper sheet, to which is bonded both the package's semiconductor chip and circuitized substrate members. The chip is bonded using a thermally conductive adhesive while the circuitized substrate, preferably a flexible circuit, is bonded using an electrically insulative adhesive. The chip is electrically coupled to designated parts of the circuitry of the substrate, preferably by wire, thermocompression or thermosonic bonding. An encapsulant may be used to cover and protect the connections between the chip and substrate. This package may in turn be electrically coupled to a separate, second substrate such as a PCB.

Abstract: A semiconductor device includes a package containing a semiconductor element disposed on a die pad, and a plurality of leads extending from an inside of the package to an outside of the package. The plurality of leads are arranged up and down in a staggered manner, an interval between ends of lower stage leads in the package is narrower than a width of upper stage leads, and ends of the lower stage leads in the package are positioned nearer to the die pad than ends of the upper stage leads.

Abstract: A plastic package for microwave applications up to 14 Ghz is disclosed. The plastic package includes a plastic platform, a lead frame embedded on the surface of the platform and, in one embodiment, a plastic cap mounted on the platform so as to seal the chip within the package. The lead frame includes a baseplate for mounting at least one semiconductor chip, at least one ground lead attached to the baseplate and extending outwardly therefrom, and at least one signal lead for conducting signals to or from such semiconductor chip. The signal lead and at least one ground lead are configured as a microwave transmission line such as microwave coplanar strips, or microwave coplanar waveguide for transmitting microwave frequency signals. The package offers a low inductance ground path, good thermal characteristics, and low parasitic inductance and capacitance. It can be applied for high speed and high frequency applications.

Abstract: A semiconductor laser device includes a base, a semiconductor laser chip and a resin layer enclosing the laser chip. The base may have a monitor photodiode mounted thereon in the vicinity of the laser chip. The resin layer enclosing the laser chip or both of the laser chip and the monitor diode chip is made of a single synthetic resin having a thickness not greater than 500 .mu.m and also having a surface substantially parallel to an outwardly oriented beam emitting end face of the laser chip.