Abstract: A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which con

Abstract: A highly reliable semiconductor device and a method of manufacturing the same. The semiconductor device is constituted by a semiconductor element which is disposed within a space portion defined by leads of a lead frame or fixed to a die pad of a lead frame and which has bonding pads connected to the leads through wires respectively, and a heat radiation block/plate which is made of a good thermally conductive material and which has an outer periphery having a size sufficiently to overlap the leads so that the heat radiation block/plate is disposed on the leads partly through a tape-like insulator, the semiconductor element being disposed on a center portion of the heat radiation block/plate directly or through the die pad. The semiconductor device is sealed with resin or the like with part of the leads and an end surface of the heat radiation block/plate left exposed or with part of the leads left exposed.

Abstract: The present invention is directed to improving the throughput of the process for fabricating multilayer interconnects. Tungsten plugs, formed in contact/via openings etched in an interlayer dielectric, have been widely used in industry to form interconnection between different metal layers. An adhesion layer comprising a Ti/TiN stack is typically employed to support the adhesion of the tungsten plug in the contact/via openings. The present invention is directed to a process involving the formation of a Ti/TiN landing pad at the base of contact/via openings prior to the deposition of the interlayer dielectric. The process of the present invention enables the removal of the Ti under-layer and the reduction of the TiN thickness in the Ti/TiN stack. The throughput of the process for fabricating multilayer interconnects is thus greatly improved while the integrity of the devices are maintained.

Abstract: A package for a semiconductor die having a plurality of bonding pads about its periphery is provided. The package has a plastic molding encapsulating the semiconductor die. The package also has a plurality of conductive leads with leads having inner and outer portions, the inner portions encapsulated in the molding and arranged substantially in a plane and radially about the semiconductor die with ends displaced from and forming a rectangle with four corners about the die. A bonding wire extends from each of the bonding pads to one of the inner portions of the leads. Bonding wire loop heights of approximately 8 mils are made with a specially designed tip of a capillary tool. The package also has a pair of leads with inner portions at opposite corners of the rectangle, each of the inner portions connected to a pair of bonding wires from a pair of contiguous bonding pads on the die. This double wiring arrangement prevents wire sweep during the injection molding step.

Abstract: A multilayered interconnection of a semiconductor device includes a substrate, an underside interconnection layer formed on the substrate, an interlayer insulation film formed on the underside interconnection layer, an upperside interconnection layer formed on the interlayer insulation film, a contact hole formed through the upperside interconnection layer and into the interlayer insulation film, and a plug formed in the contact hole so that the plug contacts an upper part of the underside interconnection layer and a side of the upperside interconnection layer.

Abstract: A method of forming a barrier layer for preventing the diffusion of a metal interconnect through an interlayer dielectric of an integrated circuit and to act as an etch stop. A thin metal layer is formed on the interlayer dielectric and then oxidized to form a metal-oxide barrier layer.

Abstract: A semiconductor integrated circuit device is provided for high-frequency or high-speed circuitry having stabilized characteristics and reduced influence on surrounding devices. In the device structure, ground leads extending from a metal substrate or metal layer for mounting ICs for high-frequency or high-speed circuitry are disposed adjacent to at least one side of signal leads and a width W or a space S of at least a part of the leads are set to inherent values for reducing the inductance of ground leads. Further, passive circuit chips for short-circuiting or blocking a high frequency signal are mounted on the metal substrate to suppress high-frequency component signals flowing through power supply leads and ground leads.

Abstract: A thin IC card includes a circuit board on which functional parts are mounted and a through-hole defining an edge of a battery lodging section in which a battery is disposed, the circuit board being embedded in a molding-resin section with the reverse surface of the board exposed. The battery lodging section is aligned with the through-hole of the circuit board. Electrical connections between the circuit board and the battery are effected in a recess or cutouts in the circuit board. The battery is embedded in the lodging section using an expandable resin to make the card surface flat.

Abstract: The present invention relates to a semiconductor package having lead pins of lead frame for outwardly extending terminals of electrodes of a semiconductor chip embedded in a mold resin. The semiconductor package according to the present invention comprises flat lead fins connected to respective sides of a bed portion of a lead frame, an insulation film for covering at least one side of each of the lead fins, and lead pins formed on a surface of the insulation film, the lead pins being disposed at a predetermined pitch.

Abstract: The invention is to a semiconductor package and the method of making the package. A moisture resistant coating such as a ceramic material is applied over a plastic packaged semiconductor device to seal the package from moisture.

Abstract: A semiconductor fuse and method for fabricating the same An insulating layer is provided and a trench formed therein. A fusible link is then formed across the insulating layer and trench and conformal therewith. The link has a break region of minimum thickness and width at an intersection of a sidewall and bottom surface of the trench.

Abstract: A barrier metal integrated circuit structure, including relatively thin, highly nitrided layers of TiW (i.e., TiW:N) straddling a central conductor layer, and in turn each being straddled by adjacent layers of relatively thick substantially un-nitrided TiW material, and a method for its fabrication including deposition of layers of TiW and TiW:N, the latter in a N.sub.2 dominated atmosphere and/or under backbias conditions effective for establishing at least a saturated level of nitrogen into the TiW:N, resulting in an effective barrier to migration of conductor materials from the conductor layer.

Abstract: A semiconductor device for life enhancement of electrical connections between a semiconductor chip and a mounting substrate. Protruding electrodes, each including a bump electrode and a land electrode, are located on the lower surface of an LSI chip. The bump electrodes are substantially spherical and have a first thickness. Connecting terminals of substantially spherical configuration and having a second thickness are directly connected to corresponding land electrodes by melting. Connecting patterns are located on the upper surface of a wiring board which is larger in area than the LSI chip in plan configuration, and external electrodes, each including a connecting pattern and an external electrode, are located on the lower surface of the wiring board. The external electrodes are substantially spherical and have a third thickness. The connecting patterns are directly connected to corresponding connecting terminals, respectively, by melting.

Abstract: A diamond heat sink of the present invention comprises:a support layer consisting of substantially undoped vapor phase synthetic diamond;a heat sensitive layer consisting of doped vapor phase synthetic diamond formed on the surface of the support layer;an insulation layer consisting of substantially undoped vapor phase synthetic diamond formed on a predetermined region of the heat sensitive layer; andan electrode formed on the heat sensitive layer. The electrode typically consists of a metal, preferably Ti/Mo/Au or Ti/Pt/Au.The diamond heat sink of the present invention may further include a highly-doped layer for creating Ohmic contacts with the metal electrode, which is made of the vapor phase synthetic diamond having high impurity levels, and which is disposed between the metal electrode and the heat sensitive layer.

Abstract: An input-output wiring for the power circuit and a ground layer are formed on a metal substrate of a power hybrid integrated circuit apparatus. A plurality of windows are opened at predetermined positions of a circuit substrate to which electronic parts such as an IC driver, a chip resistor etc. are connected. Ceramic chips are soldered on the exposed surface of the metal substrate in the windows, and the power semiconductor elements are connected through metal bridges on the ceramic chips. Connection between lower electrode of adjoining power semiconductor elements or between lower part of the power semiconductor element and an input/output wiring is made by means of a part of the metal bridge.

Abstract: An improved semiconductor module comprising a molded frame and a composite semiconductor substrate subassembly received in a cavity in said frame. The composite semiconductor substrate subassembly comprises a plurality of semiconductor devices which are connected to electrical contacts on an edge of the molded frame by a variety of configurations described herein. In one embodiment of the invention, the composite semiconductor substrate sub-assembly includes a composite substrate which comprises a thin metal cover plate and thin laminate circuit which is bonded to the metal cover plate by a film adhesive. The composite substrate provides a mounting surface for the placement of semiconductor devices and their associated passive components.

Abstract: High conductivity interconnection lines are formed of high conductivity material, such as copper, employing barrier layers impervious to the diffusion of copper atoms. Higher operating speeds are obtained with conductive interconnection lines, preferably copper interconnection lines, formed above the wire bonding layer.

Abstract: A composite containing an integrated circuit chip having conductive site thereon and electrically conductive leads that are interconnected to the conductive site by electrically conductive wire; wherein the wire is coated with a dielectric material. Also, a method for fabricating the composite is provided.

Abstract: An LED lamp arrangement has at least one pair of lead terminals, an LED element attached to an end of one lead terminal, a metal wire connecting the LED element to the other lead terminal, a light-transmitting molded portion sealingly enclosing the ends of the lead terminals and the LED element, and a black coating on a rear surface of the molded portion to enhance recognition of the lighted condition of the LED lamp.

Abstract: A semiconductor package stack assembly providing reduced electrical noise, in which a conductive film is provided on an exposed bottom surface of the semiconductor chip of each semiconductor package in a unitary stack thereof, each conductive film being grounded to ground lines of the printed circuit board on which the lowermost package of the stack is surface-mounted.