Patents Examined by T. M. Arroyo
  • Patent number: 5726501
    Abstract: A semiconductor device according to the present invention to be mounted on a mounting substrate includes: a connection electrode formed on a surface of the semiconductor device; a solder bump formed on the connection electrode, the solder bump electrically and mechanically connecting the connection electrode with a substrate electrode formed on the mounting substrate; and a solder drawing layer provided on the surface of the semiconductor device in a periphery of the solder bump and having a surface portion composed of a solder-agreeable metal, the solder drawing layer retracting melted solder of the solder bump onto a surface of the solder drawing layer by contact with the melted solder.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: March 10, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroshi Matsubara
  • Patent number: 5726498
    Abstract: Capacitive coupling, and attendant cross-talk, is reduced by increasing the distance between wire surfaces in integrated circuit applications. This is done by changing wire shape from the conventional rectangular cross-section. A cross-section which consists of a rectangular portion and a shaped, triangular portion is created, having the effect of increasing the effective distance between adjacent conductors. Cross-sectional area of wires is maintained and thus the current carrying capacity is maintained. The wire shapes may be produced using several alternate methods.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: March 10, 1998
    Assignee: International Business Machines Corporation
    Inventors: Thomas John Licata, Jack Allan Mandelman
  • Patent number: 5723901
    Abstract: A semiconductor device for reducing the mounting area of semiconductor chips on the mounting substrate includes a first base substrate made of an insulating material, a semiconductor chip mounted on the first base substrate, a plurality of internal wiring elements disposed on the first base substrate, and a plurality of bonding elements respectively connecting the semiconductor chip and the internal wiring elements. A second base substrate made of an insulating material is disposed on the first base substrate, and a resin seals the semiconductor chip and the bonding elements. A plurality of lower electrodes are formed on a lower surface of the first base substrate, a plurality upper electrodes are formed on an upper surface of the second base substrates, and a plurality of through holes respectively connecting one of the lower electrodes to one of the upper electrodes are formed on an external side surface of the first and second base substrate.
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: March 3, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akio Katsumata
  • Patent number: 5723899
    Abstract: A lead frame for semiconductor packages is disclosed. In the lead frame, some of the inner leads in the four sides are extended and provided with connection bars on their inside ends. Alternatively, diagonally arranged tie bars of the lead frame are extended and provided with a rectangular guide ring on their inside ends. The connection bar or guide ring functions as a dam for restricting possible overflow of adhesive, which adhesive is applied on the heat sink for bonding a semiconductor chip to the heat sink. The lead frame of the invention also prevents waste of expensive tape by letting the adhesive tape adhere only to the connection bars or to a given portion of the guide ring when mounting the lead frame to the heat sink and makes it possible higher integration of semiconductor chip by making connection bar and guide ring from the lead or the tie bar.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: March 3, 1998
    Assignees: Amkor Electronics, Inc., Anam Industrial Co., Ltd.
    Inventor: Won Sun Shin
  • Patent number: 5723907
    Abstract: A lead-over-chip single-in-line memory module (LOC SIMM) and method of manufacturing is disclosed that provides for shortened wire bonds and ease of rework for unacceptable semiconductor dice. More specifically, the LOC SIMM of the present invention includes a plurality of slots extending through a circuit board with an equal number of semiconductor dice attached thereto such that the active surfaces of the dice are exposed through the slots. Wire bonds or TAB connections are made from the exposed active surface of the die, through the slot, and to contacts on the top surface of the circuit board. Dice proven unacceptable during burn-in and electrical testing of the module are replaced by known good dice (KGD) by breaking their respective wire bonds, attaching a KGD to the circuit board, and forming new electrical connections between the KGD and the circuit board.
    Type: Grant
    Filed: June 25, 1996
    Date of Patent: March 3, 1998
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 5717255
    Abstract: A semiconductor device has a semiconductor element, an output terminal coupled to the semiconductor element and a thin metal member or foil secured to an output terminal. A protective layer covers the semiconductor element including the periphery of the metal foil to define an opening located at the metal foil. By covering the periphery of the metal foil, the protective layer secures the metal foil to the semiconductor element. A lead element is affixed to the metal foil by soldering through the opening. The resulting structure increases the adhesion of the lead element. Furthermore, because the protective film covers and seals the periphery of the metal foil, the advance of moisture into the inside of the semiconductor device is retarded. Accordingly the moisture resistance of the semiconductor device is improved.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: February 10, 1998
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Takahiro Haga, Yoshinori Kaido, Takayoshi Yasuda
  • Patent number: 5717246
    Abstract: A hybrid lead frame having leads for conventional lead-to-I/O wire bonding, and leads for power and ground bussing that extends over a surface of the semiconductor die are provided where the leads for bussing are held in place by lead-lock tape to prevent bending and/or other movement of the bussing leads during manufacturing. More specifically, the lead-lock tape is transversely attached across a plurality of bussing leads proximate to and outside of the position where the die is to be attached.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: February 10, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Jerry M. Brooks, Larry D. Kinsman, Timothy J. Allen
  • Patent number: 5717248
    Abstract: Cooling and screening device for integrated circuits, have a metal plate (26) having integrally formed cooling projections (28) and having bores (34) extending from the upper side and bottom side of the metal plate (26). Inserted into these bores (34) are contact pins (39) whose free ends form soldering tips (38) which are intended for soldering into plated-through bores (40) of a printed circuit board (20).
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: February 10, 1998
    Assignee: Siemens Nixdorf Informationssysteme AG
    Inventors: Gerd Neumann, Hans-Jorg John, Horst Weege
  • Patent number: 5714795
    Abstract: A semiconductor storage device capable of high-speed writing and reading and having extremely high reliability. The semiconductor device includes a plurality of cells each having a semiconductor layer between a pair of conductors. At least one of the pair of conductors is made of a metal and the semiconductor layer is made of a-Si which forms a silicide region having a width of 150 nm or less by silicide reacting with the metal at a reaction speed of 10 m/sec or higher. Alternatively, at least one of the pair of conductors is made of a metal which silicide reacts with a-Si to form a silicide region having a conical structure with a diameter of 150 nm or less. Otherwise, at least one among the pair of conductors is formed of a metal which forms a silicide region of 150 nm or less by reacting with a-Si. The interface between the semiconductor layer and the conductors is not exposed to an external oxygen containing atmosphere during processing so that no oxygen containing compound exists at this interface.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: February 3, 1998
    Assignee: Tadahiro Ohmi
    Inventors: Tadahiro Ohmi, Hiroshi Suzuki, Masaki Hirayama
  • Patent number: 5712508
    Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a "strapping" via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: January 27, 1998
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Kyle W. Terrill
  • Patent number: 5710460
    Abstract: A method and structure for reducing short circuits in semiconductor devices is disclosed. A three layer interlevel dielectric structure is formed over a semiconductor substrate, which typically comprises a first metallization level, M1. The three layer dielectric includes a first insulator layer, a middle spin-on glass (SOG) layer, and a top second insulator layer. The spin-on glass fills defects in the surface of the first insulator layer created during planarization using chemical-mechanical-polishing (CMP). Prior to deposition of the second insulator, a first via is etched through the SOG film and the first insulator layer to expose a portion of the semiconductor substrate, typically a conductive metal. A conductive metal is deposited into the first via and planarized to form a metal interconnection stud. Because the surface defects are filled and covered with the SOG film, none of the deposited metal enters the defects, and short circuits with the stud are greatly reduced.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: January 20, 1998
    Assignee: International Business Machines Corporation
    Inventors: Robert Kenneth Leidy, Jeffrey Scott Miller, Jon A. Patrick, Rosemary Ann Previti-Kelly
  • Patent number: 5708297
    Abstract: An improved multichip semiconductor module compatible with existing SIMM memory sockets comprising a molded module frame and a composite semiconductor substrate subassembly received in a cavity in said frame. The composite semiconductor substrate subassembly or subassembly(s) comprises a plurality of semiconductor devices which are connected to electrical contacts on an edge of the molded frame by a variety of configurations described herein. In one embodiment of the invention, the subassembly(s) includes a composite substrate which comprises a thin metal cover plate and thin laminate circuit which is bonded to the metal cover plate by a film adhesive. The composite substrate provides a mounting surface for the placement of semiconductor devices and their associated passive components.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: January 13, 1998
    Inventor: James E. Clayton
  • Patent number: 5708298
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: January 13, 1998
    Assignees: Hitachi Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics, Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Patent number: 5708294
    Abstract: A lead frame has a frame section for carriage, a square die pad for mounting a semiconductor chip, and four suspension arms bridging the frame section and corners of the die pad. The die pad has a plurality of oblique slits therein extending parallel to one another and parallel to a diagonal line of the die pad passing first and second corners of the die pad. During encapsulation, resin is introduced from a gate of molding dies located at the first corner to a vent of the molding dies located at the second corner. The oblique slits enhances oblique resin-flow under the lower surface of the die pad during encapsulation of the semiconductor device, to thereby prevent a die pad shift, unfilling of the resin and resin void in the semiconductor device.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: January 13, 1998
    Assignee: NEC Corporation
    Inventor: Keiji Toriyama
  • Patent number: 5708304
    Abstract: A semiconductor device is reduced in size and has a highly warp resistant structure. A sealing resin formed by transfer molding covers a whole semiconductor chip including pad electrodes, connecting bumps, an upper surface of a wiring board including a plurality of chip connecting patterns, a side surface of the wiring board, and a peripheral area of a lower surface of the wiring board surrounding an area where external electrode portions are located. The wiring board is substantially coextensive in an area with the semiconductor chip in plan configuration. The area occupied by the external electrode portions is smaller than the area occupied by the chip connecting patterns.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: January 13, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yoshihiro Tomita
  • Patent number: 5705851
    Abstract: A Thermal Ball Lead Integrated Package (Thermal BLIP) having improved thermal performance over prior art BLIPs is described. The BLIP combines ball and lead technologies to increase the interconnect density of the package but has relatively poor heat extraction capabilities. The Thermal BLIP is particularly well suited for high power and pin count integrated circuit devices. In an embodiment of the present invention, a heat sink is attached to the top surface of the die and extends through the package molding such that it is exposed to the ambient environment. Since the heat sink is integrated into the molding, the package size and footprint is not increased thereby limiting the cost increase of the package. This arrangement enables the use of high power devices in dense circuit board applications.
    Type: Grant
    Filed: June 28, 1995
    Date of Patent: January 6, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Shahram Mostafazadeh, Satya Chillara, Jagdish G. Belani
  • Patent number: 5705858
    Abstract: A packaging structure for a semiconductor device has plural hermetically sealed units each containing a flip-chip electrically interconnected to an intermediate substrate, circuit patterns of the flip-chips being within the sealed environment. Each hermetically sealed unit is connected to a base wiring substrate through soldered electrodes. Replacement of a flip-chip is accomplished by melting the solder joints between the flip-chip's respective hermetically sealed unit and the base wiring substrate. The flux vapor given off during this replacement process does not damage the circuit patterns of nearby flip-chips because they are contained in a sealed environment. Additionally, the electrodes between the flip-chips and intermediate substrate and between intermediate substrates and the base wiring layer contain projections which prevent crushing of solder between opposing electrodes and deformation of the flip-chip under a heavy load.
    Type: Grant
    Filed: April 14, 1994
    Date of Patent: January 6, 1998
    Assignee: NEC Corporation
    Inventor: Kenji Tsukamoto
  • Patent number: 5703401
    Abstract: The invention relates to a semiconductor device for surface mounting with a substrate carrier having a surface provided with a groove with walls on which conductor tracks are present, which conductor tracks continue on the surface of the substrate carrier and form connection conductors of the device which is provided with a semiconductor element arranged in the groove with its main surface parallel to a wall which semiconductor element makes electrical contact with the conductor tracks on the wall, while the groove is filled with a protective material and the substrate carrier is provided with a side wall interconnecting mutually opposed walls of the groove on either side of the semiconductor element.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: December 30, 1997
    Assignee: U.S. Philips Corporation
    Inventors: Peter W. M. van de Water, Roelf A. J. Groenhuis, Cornelis G. Schriks
  • Patent number: 5703395
    Abstract: An electronic miniaturized memory device according to the invention has at least one integrated memory circuit (2,20) and an interconnection interface (3), said memory device comprises a case (1) being a housing for an electronic subsystem (17), said interconnection interface (3) comprises at least one central contact (7,70) for electrically contacting at least one integrated memory circuit (2,20) and said case (1) comprises projecting portion (14) facilitating the attaching of the memory device to a support (8), allowing the memory device to document information relative to the curriculum vitae of the support (8) or to elements in its environment.
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: December 30, 1997
    Assignee: Gay Freres S.A.
    Inventor: Jean-Claude Berney
  • Patent number: 5703402
    Abstract: The present invention relates to a substrate for ball-grid arrays. Bond sites are arranged around a die-attach region of the substrate. Signal traces connect the bond sites to vias disposed on the substrate, thus providing an electrical path between both sides of the substrate. Solder balls (solder bumps) are disposed on the other side of the substrate and arranged in a grid-like pattern. The generally linearly-arranged bond sites are sequentially numbered, as is the grid-like arrangement of solder balls. In a preferred embodiment, the bond sites are used only for carrying signals to and from the semiconductor die. In addition, only the solder bumps used for carrying signals are sequentially numbered. In another embodiment of the invention, some of the bond sites may be used for utilities such as ground and power. Such utility bond sites are not numbered. Likewise, utility solder balls are not numbered. The signal bond sites are coupled to vias by signal traces.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: December 30, 1997
    Assignee: ACC Microelectronics Corporation
    Inventors: Edwin Chu, Hu-Kong Lai