Patents Examined by T. N. Quach
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Patent number: 6717268Abstract: Metallic reservoirs in the form of passive or dummy vias are used on interconnects as a source or sink for electromigration material, slowing the build up of electromigration-induced mechanical stress. The passive or dummy vias are disposed in a vertical direction from the interconnect (perpendicular to the plane of the interconnect) to so that the reservoirs do not occupy additional space in the interconnect layer. Both apparatus and method embodiments are described.Type: GrantFiled: November 13, 2001Date of Patent: April 6, 2004Assignee: Intel CorporationInventor: Stefan P. Hau-Riege
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Patent number: 6716737Abstract: A method of forming a through-substrate interconnect for a circuit element in a microelectronics device is provided. The device is formed on a substrate having a frontside and a backside, and includes a circuit element formed on the frontside of the substrate connected to a contact pad formed on the backside of the substrate by the through-substrate interconnect. The method includes forming a first interconnect structure extending into the substrate from the frontside of the substrate, at least partially forming the circuit element such that the circuit element is in electrical communication with the first interconnect structure, and forming a second interconnect structure extending into the substrate from the backside of the substrate after forming the first interconnect structure such that the second interconnect structure is in electrical communication with the first interconnect structure.Type: GrantFiled: July 29, 2002Date of Patent: April 6, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: Hubert Vander Plas, Barry C. Snyder, Ronald A. Hellekson, Ronnie J. Yenchik, Diane Lai, Samson Berhane
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Patent number: 6716682Abstract: A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.Type: GrantFiled: October 10, 2002Date of Patent: April 6, 2004Assignee: Micron Technology, Inc.Inventor: Chandra V. Mouli
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Patent number: 6713384Abstract: A method of making a contact plug and a metallization line structure is disclosed in which a substrate is provided with at least one contact hole within an insulation layer situated on a semiconductor substrate of a semiconductor wafer. A first metal layer is deposited upon the semiconductor wafer within the contact hole. A planarizing step isolates the first metal layer within the insulation layer in the form of a contact plug within the contact hole. A second metal layer is then deposited upon the semiconductor wafer over and upon the contact plug. Metallization lines are patterned and etched from the second metal layer. The contact hole may also be lined with a refractory metal nitride layer, with a refractory metal silicide interface being formed at the bottom of the contact hole as an interface between the contact plug and a silicon layer on the semiconductor substrate.Type: GrantFiled: January 16, 1998Date of Patent: March 30, 2004Assignee: Micron Technology, Inc.Inventors: Richard L. Elliott, Guy F. Hudson
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Patent number: 6713835Abstract: A method for forming interlevel dielectric layers in multilevel interconnect structures using air as the constituent low-k dielectric material that is compatible with damascene processes without introducing additional process steps. The conductive features characteristic of the damascene process are formed by standard lithographic and etch processes in the mandrel material for each level of the interconnect structure. The conductive features in each level are surrounded by the mandrel material. After all levels of the interconnect structure are formed, a passageway is provided to the mandrel material. An isotropic etchant is introduced through the passageway that selectively etches and removes the mandrel material. The spaces formerly occupied by the mandrel material in the levels of the interconnect structure are filled by air, which operates as a low-k dielectric material.Type: GrantFiled: May 22, 2003Date of Patent: March 30, 2004Assignee: International Business Machines CorporationInventors: David Vaclav Horak, Charles William Koburger, III, Peter H. Mitchell, Larry Alan Nesbit
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Patent number: 6709970Abstract: A method for forming void-free, low contact-resistance damascene interconnects during a manufacturing process of an integrated circuit having both narrow and deep openings and wide and shallow openings on a same substrate features a two-step copper (Cu) deposition process, with a high-temperature rapid annealing process being conducted after the first deposition. After forming in a top surface a narrow and deep opening and a wide and shallow opening, a first copper (Cu) layer is deposited on a seed layer using a small-grained Cu material to completely fill the narrow and deep opening. After annealing the first Cu layer to reduce stress on the resulting structure, a second layer of large-grained Cu material is deposited on the annealed first Cu layer to fill the remainder of the openings. The resulting assembly, which requires no additional annealing, is then planarized to the original surface.Type: GrantFiled: September 3, 2002Date of Patent: March 23, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chankeun Park, Sangrok Hah, Juhyuck Chung, Hongseong Son, Byunglyul Park
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Patent number: 6709974Abstract: A method of preventing seam defects on narrow, isolated lines of 0.3 micron or less during CMP process is provided. The solution is to change the size of features of dummy metal structures on the same layer as the metal layer to have a width that is about 0.6 micron or less so that during the electroplating the deposition rate in the features is similar to the narrow, isolated lines. The density, shape, and proximity of the dummy metal structures further prevents the seam defects during CMP processing by preventing Galvanic corrosion.Type: GrantFiled: December 19, 2002Date of Patent: March 23, 2004Assignee: Texas Instruments IncorporatedInventors: David Permana, Jiong-Ping Lu, Albert Cheng, Jeff A. West, Brock W. Fairchild, Scott A. Johannesmeyer, Chris M. Bowles, Thomas D. Bonifield, Rajesh Tiwari
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Patent number: 6700142Abstract: The present invention provides a semiconductor wafer that has a predetermined global functionality and comprises a top surface, a bottom surface and a peripheral edge between the top surface and the bottom surface. An integrated circuit is fabricated on the semiconductor wafer and includes a working set of discrete functional modules arranged into a central rectangular array of rows and columns defined by a boundary that includes four rectilinear sides and four corners. The integrated circuit further includes a spare set of discrete functional modules formed outside the boundary of the working set into at least one line that is disposed along a side of the rectangular array of the working set. If a discrete functional module in the working set is found to be defective, it can be replaced by a discrete functional module in the spare set.Type: GrantFiled: December 30, 2002Date of Patent: March 2, 2004Assignee: Hyperchip Inc.Inventor: Richard S. Norman
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Patent number: 6699746Abstract: The present invention discloses a method for manufacturing a semiconductor device. In the method for manufacturing the semiconductor device, a contact plug connected to a predetermined region for a bit line contact and a storage electrode contact is formed in a cell region of a semiconductor substrate before a source/drain region is formed in a peripheral circuit region of the semiconductor substrate using an epitaxially grown silicon film in a high temperature process, to obtain a contact plug having a high filling characteristic and a low contact resistance. In addition, additional ion-implantation process of a P type impurity in the subsequent bit line contact formation can be omitted to simplify the fabrication process. The method is suitable for the high speed merged DRAM logic process to achieve the high speed operation of the semiconductor device, and improves a process yield and reliability of the semiconductor device.Type: GrantFiled: December 27, 2002Date of Patent: March 2, 2004Assignee: Hynix Semiconductor Inc.Inventors: Su Ock Chung, Sang Don Lee
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Patent number: 6696339Abstract: The present invention is directed toward methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. One embodiment of the method includes constructing bit line contact openings in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. The method also includes depositing a first conductive material into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. This embodiment continues by forming a trench through an upper portion of a plurality of the bit line contacts and portions of the dielectric layer between bit line contacts.Type: GrantFiled: August 21, 2002Date of Patent: February 24, 2004Assignee: Micron Technology, Inc.Inventor: Sang Dang Tang
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Patent number: 6686241Abstract: The method applies to non-volatile semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal, a second terminal, and a third terminal connected, respectively, to a row line, to a column line, and to a common node by respective connection strips. In order to form connections with low resistivity and consequently to save semiconductor area, the method provides for the formation of an oxide layer which covers the connection strips of the first terminals and of the third terminals, the formation of channels along the connection strips until the surfaces thereof are exposed, and the filling of the channels with a material having a resistivity lower than that of the connection strips.Type: GrantFiled: March 2, 2001Date of Patent: February 3, 2004Assignee: STMicroelectronics S.r.l.Inventors: Massimo Ati, Alfonso Maurelli, Nicola Zatelli
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Patent number: 6680238Abstract: A method for manufacturing a semiconductor device includes the steps of: sequentially forming a pad oxide layer, a nitride layer and a first photoresist layer on the semiconductor substrate; patterning the first photoresist layer into a predetermined shape to form a first photoresist layer pattern; etching the pad oxide layer, the nitride layer and the semiconductor substrate by using the first photoresist layer pattern as an etching mask, thereby forming first and second deep trench isolations in the semiconductor substrate; forming a barrier layer on an inside wall of the second deep trench isolation by performing a nitriding process after removing the first photoresist layer pattern and forming a second photoresist layer pattern at a region formed with the first deep trench isolation on the resultant material; and forming a shallow trench isolation by removing the second photoresist layer pattern and then growing silicon in the first deep trench isolation region covered with the second photoresist layer paType: GrantFiled: December 17, 2002Date of Patent: January 20, 2004Assignee: Hynix Semiconductor Inc.Inventor: Woon-young Song
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Patent number: 6677680Abstract: A metal wiring plus low-k dielectric interconnect structure of the dual damascene-type is provided wherein the conductive metal lines and vias are built into a hybrid low-k dielectric which includes two spun-on dielectrics that have different atomic compositions and at least one of the two spun-on dielectrics is porous. The two spun-on dielectrics used in forming the inventive hybrid low-k dielectric each have a dielectric constant of about 2.6 or less, preferably each dielectric of the hybrid structure has a k of from about 1.2 to about 2.2. By utilizing the inventive hybrid low-k dielectric excellent control over metal line resistance (trench depth) is obtained, without no added cost. This is achieved without the use of a buried etch stop layer, which if present, would be formed between the two spun-on dielectrics.Type: GrantFiled: February 28, 2001Date of Patent: January 13, 2004Assignee: International Business Machines CorporationInventors: Stephen McConnell Gates, Jeffrey Curtis Hedrick, Satyanarayana V. Nitta, Sampath Purushothaman, Cristy Sensenich Tyberg
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Patent number: 6673682Abstract: Methods for making integrated circuit devices, such as high density memory devices and memory devices exhibiting dual bits per cell, include forming multiple oxide fences on a semiconductor substrate between multiple polybars. The oxide fences create a hole pre-code pattern that facilitates ion implantation into trenches disposed between the polybars. The holes, or voids, formed by the oxide fences provide greater control of the critical dimension of ion implantation, for example, the critical dimension of the trench sidewalls. Semiconductor devices used in the manufacture of memory devices include the oxide fences during the manufacturing process.Type: GrantFiled: May 13, 2002Date of Patent: January 6, 2004Assignee: Macronix International Co. Ltd.Inventor: Ching-Yu Chang
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Patent number: 6664170Abstract: The present disclosure relates to a method for forming a device isolation layer of a semiconductor device by a shallow trench isolation (STI). In the disclosed methods, after a nitride layer is removed from the silicon substrate, an amorphous silicon layer is deposited thereon and is oxidized to form an amorphous spacer at a side wall of the device isolation layer by etching the amorphous silicon layer.Type: GrantFiled: January 13, 2003Date of Patent: December 16, 2003Assignee: Hynix Semiconductor, Inc.Inventor: Won-kwon Lee
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Patent number: 6660576Abstract: A substrate and a method for fabricating variable quality substrate materials are provided. The method comprises: selecting a first mask having a first mask pattern; projecting a laser beam through the first mask to anneal a first area of semiconductor substrate; creating a first condition in the first area of the semiconductor film; selecting a second mask having a second mask pattern; projecting the laser beam through the second mask to anneal a second area of the semiconductor film; and, creating a second condition in the second area of the semiconductor film, different than the first condition. More specifically, when the substrate material is silicon, the first and second conditions concern the creation of crystalline material with a quantitative measure of lattice mismatch between adjacent crystal domains.Type: GrantFiled: March 11, 2002Date of Patent: December 9, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Apostolos Voutsas, Yasuhiro Mitiani, Mark A. Crowder
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Patent number: 6660590Abstract: The present invention discloses a vertical transistor wherein source/drain regions are formed by using a self-alignment method without using a latest photolithography, channels are formed via a selective epitaxial growth (hereinafter, referred to as ‘SEG’) method and gate oxide films are formed at the both ends of channels to be more efficient than devices having the same channel length, and a method of manufacturing thereof, the vertical transistor comprising: a source region formed on a semiconductor substrate; a drain region formed substantially above the source region; a vertical channel, one end of the channel being contact to the source region and the other end being contact to the drain region; and a gate electrode, formed on the substrate, surrounding the sides of the channel and the drain region, said gate electrode electrically isolated with the source region by a nitride pattern disposed therebetween, isolated with the drain region by a nitride spacer formed on the sidewalls of the draiType: GrantFiled: December 27, 2002Date of Patent: December 9, 2003Assignee: Hynix Semiconductor Inc.Inventor: Kyung Dong Yoo
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Patent number: 6657223Abstract: A strained silicon MOSFET utilizes a strained silicon layer formed on a silicon germanium layer. Strained silicon and silicon germanium are removed at opposing sides of the gate and are replaced by silicon regions. Deep source and drain regions are implanted in the silicon regions, and the depth of the deep source and drain regions does not extend beyond the depth of the silicon regions. By forming the deep source and drain regions in the silicon regions, detrimental effects of the higher dielectric constant and lower band gap of silicon germanium are reduced.Type: GrantFiled: October 29, 2002Date of Patent: December 2, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Haihong Wang, Qi Xiang
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Patent number: 6656783Abstract: A semiconductor device having a shallow trench isolation (STI) structure, which is capable of reducing leakage current in a P-FET and improving the device characteristics of a memory device, and a manufacturing method thereof, including a semiconductor substrate having a first area with a first trench formed therein and a second area with a second trench formed therein; a first sidewall oxide layer formed on the inner surface of the first trench; a second sidewall oxide layer, which is thinner than the first sidewall oxide layer, formed on the inner surface of the second trench; a liner formed on the surfaces of the first and second sidewall oxide layers; and a dielectric material that fills the first and second trenches.Type: GrantFiled: September 25, 2002Date of Patent: December 2, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Joo-Wook Park
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Patent number: 6653223Abstract: Within a method for forming a dual damascene aperture within a microelectronic fabrication, there is employed a patterned first dielectric layer which defines at least part of a via. The patterned first dielectric layer in turn has formed thereover a blanket second dielectric layer formed such as to form a void at the location of the via and thus form an incompletely filled via. Thus when forming a trench within the blanket second dielectric layer contiguous with a re-opened via formed from the incompletely filled via, the void provides for enhanced dimensional control when forming the re-opened via from the incompletely filled via.Type: GrantFiled: July 9, 2002Date of Patent: November 25, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventor: Leder Shiu