Abstract: A method of substantially reducing and/or eliminating the amount of defects and/or impurities that amass at interfacial surfaces that are present in a multilayer structure is provided. Specifically, the method improves the efficiency of a forming gas anneal by providing a multilayer structure having a catalytic layer formed thereon or buried therein which allows for a significant increase in the amount of hydrogen or deuterium which can be incorporated into the structure. The method is also conducted at a low temperature (on the order of about 400° C. or less). Multilayer structures are also provided which include an annealed multilayer structure having at least one interfacial surface present therein. The at least one material interface contains a region of hydrogen or deuterium which substantially reduces defects and impurities present at the at least one interface.

Abstract: The barrier material of the invention provides for the electrodeposition of copper. The barrier layer includes a dielectric interface surface region, and a copper interface surface region with at least 50 atom percent of a copper interface metal. In particular, the barrier layer of the invention provides for the electrodeposition of copper or copper alloy directly onto the copper interface region of the barrier layer in a direct electrodeposition process. The process includes providing a dielectric layer disposed on an underlayer, contacting a barrier layer to the dielectric layer, and depositing a conducting layer onto the barrier layer.

Abstract: An insulating film with a linear concave portion is formed and a semiconductor film is formed thereon by deposition. The semiconductor film is irradiated with laser light to melt the semiconductor film and the melted semiconductor is poured into the concave portion, where it is crystallized. This makes distortion or stress accompanying crystallization concentrate on other regions than the concave portion. A surface of this crystalline semiconductor film is etched away, thereby forming in the concave portion a crystalline semiconductor film which is covered with side walls of the concave portion from the sides and which has no other grain boundaries than twin crystal. TFTs and memory TFTs having this crystalline semiconductor film as their channel regions are highly reliable, have high field effect mobility, and are less fluctuated in characteristic. Accordingly, a highly reliable semiconductor memory device which can operate at high speed is obtained.

Abstract: A light-emitting diode with enhanced brightness and a method for fabricating the diode is provided. The light-emitting diode includes an epitaxial LED structure having at least one lighting-emitting active layer with a plurality of windows formed in a highly doped layer. At least one conductive contact is formed on the bottom surface of the highly doped layer. A transparent material layer is formed in the windows. An adhesion layer is formed between the transparent material layer and a permanent substrate. A bottom electrode is formed on the bottom surface of the permanent substrate and an opposed electrode is formed on the top surface of the epitaxial LED structure.

Abstract: A random access memory cell and fabrication method therefor are disclosed. The random access memory cell includes a first and a second pull-down transistor cross-coupled such that a control terminal of the first pull-down transistor is connected to a conduction terminal of the second pull-down transistors, and the control terminal of the second pull-down transistor is connected to the conduction terminal of the first pull-down transistor. A first pass gate transistor is coupled between the conduction terminal of the first transistor and a first bit line of a bit line pair, and a second pass gate transistor is coupled between the conduction terminal of the second transistor and a second bit line of the bit line pair.

Abstract: A semiconductor component having an optical interconnect formed thereover and a method for manufacturing the semiconductor component. The semiconductor component has a transistor coupled to a light emitting device and another transistor coupled to a light detecting device by a metallization system. The light emitting device is optically coupled to the light detecting device by an optical interconnect formed over the transistors and the metallization system.

Abstract: A new method and structure for the combined creation of CMOS devices and LED devices. The process starts with a substrate over the surface of which are designated a first surface region for the creation of CMOS devices there-over and a second surface region for the creation of LED devices there-over. A relatively thick layer of gate oxide is created over the surface of the substrate. The first surface region is blocked by a mask of photoresist after which the second surface region is exposed to a plasma etch, thereby providing roughness to the surface of the relatively thick layer of gate oxide and reducing the thickness thereof. The blocking mask is removed, additional oxidation of the exposed surface creates a relatively thick layer of gate oxide over the first surface area and a relatively thin layer of gate oxide over the second surface area.

Abstract: A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface.

Abstract: A method for producing an electrode enabling fabrication of small electrodes at a high dimensional accuracy without being affected by the number of connections between chips, comprising the steps of forming an insulating film on an interconnection pattern of a semiconductor chip, forming a mask layer having an opening on the insulating film at a position where an electrode is to be formed, removing the insulating film within the opening by using the mask layer as a mask to expose a portion of the interconnection pattern, forming a conductor layer on the exposed interconnection pattern and the mask layer, removing the conductor layer formed on the mask layer while leaving the conductor layer formed on the exposed interconnection pattern, and removing the mask layer, and a method for producing a semiconductor device provided with such electrode.

Abstract: It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

Abstract: The invention concerns a method comprising evaporating silicon and/or SiOx, wherein said evaporating is further defined as occurring in the presenceof oxygen if silicon or SiOx with x less than two is being evaporated, to form a silicon oxide film at the surface of a substrate and in bombarding said silicon film, while it is being formed, with a beam of positive ions derived from both a polyfluorocarbon compound and a rare gas. The invention is useful for producing low-index antiglare films.

Abstract: To provide a method of efficiently configuring a circuit requiring high inter-device consistency by using thin-film transistors. A semiconductor layer is formed on a substrate and is patterned into desired shapes to form first semiconductor islands. The first semiconductor islands are uniformly crystallized by laser irradiation within the surface areas thereof. Thereafter, the semiconductor layers are patterned into desired shapes to become active layers of the thin-film transistors layer. Active layers of all of thin-film transistors constituting one unitary circuit are formed of one of the first semiconductor islands in this case. Thus, the TFTs mutually realize high consistency.

Abstract: As an alternative embodiment and in connection with the reduction of the amount of ammonia in the mixture, processing conditions may be altered from conditions that are less likely to cause formation to oxide husk 20 to conditions that are more likely. For example, processing temperatures sufficient to form passivation layer 32 may be initiated with an ammonia-rich mixture under conditions not likely to cause formation of oxide husk 20. As the amount of ammonia in the mixture is reduced, processing temperatures may be increased proportionally under conditions that are more likely to cause formation of oxide husk 20 than under conditions previously established when the amount of ammonia in the mixture is greater. The initial formation of some of passivation layer 32, however, resists the formation of oxide husk 20. Preferably, the processing temperature will be the same as the deposition temperature for ILD layer 18.

Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.

Abstract: A method of making an electrical contact bump electrical contact structure on a substrate comprising: providing a substrate having a bond pad, and a passivation layer overlying a portion for the substrate and wherein the passivation layer includes an opening therein exposing a portion of the bond pad, and wherein the passivation layer has a raised portion overlying the bond pad; forming an under bump metallurgy over at least the exposed portion of the bond pad and over at least a portion of the raised portion of the passivation layer overlying the bond pad; forming a sacrificial blanket having an opening therein that in cross-section has an inverted T-shape over the substrate so that the opening in the sacrificial blanket is aligned with the bond pad; and depositing an electrically conductive material into the opening in the sacrificial blanket.

Abstract: A method for image reversal in semiconductor processing includes forming a first implant mask layer upon a semiconductor substrate and forming a patterned photoresist layer over the first implant mask layer. Portions of the first implant mask layer not covered by the patterned photoresist layer are removed so as to expose non-patterned portions of the substrate. The photoresist layer is then removed, and a second implant mask layer is formed over the non-patterned portions of the substrate, wherein the first implant mask layer has an etch selectivity with respect to the second implant mask layer. The remaining portions of the first implant mask layer are removed to expose a reverse image of the substrate, including initially patterned portions of the substrate.

Abstract: A method for differentiating integrated circuits implementing identical functions by storage of a binary code in a non-volatile storage element provided in each circuit, including providing, for each circuit of a same reticle, a selective implantation of dopants of its storage element which is different from the selective implantations of dopants of the storage elements of the other circuits.

Abstract: The present disclosure provides a method and system for removing a spacer, such as associated with a processing operation using a lightly doped drain (LDD) region. The method includes defining an electrode on a substrate, forming a spacer adjacent to at least one sidewall of the electrode, and performing a processing operation on the substrate. The processing operation, which can be an ion implantation process, can use the spacer as a mask, and as a result can create a layer, such as a polymer, on the spacer. The spacer can then be removed by applying a first dry etch process to remove the layer on the spacer and a second wet etch process to remove the spacer. The first dry etch utilizes a fluorine-contained plasma, such as one that uses a CF4, CHF3, CH2F2, or CH3F etchant. A third wet etch process can be used to remove an oxide layer underlying the spacer.

Abstract: In the light emitting device having, a light emitting layer portion and a current spreading layer, respectively composed of a Group III-V compound semiconductor, formed on a single crystal substrate, the light emitting layer portion is formed on the single crystal substrate by the metal organic vapor-phase epitaxy process, and on such light emitting layer portion the current spreading layer is formed by the hydride vapor-phase epitaxy process. A high-concentration doped layer is also formed in a surficial area including the main surface on the electrode forming side of the current spreading layer, so as to have a carrier concentration of p-type dopant higher than that in the residual portion of the current spreading layer.

Abstract: High electron mobility transistors (HEMTs) and methods of fabricating HEMTs are provided Devices according to embodiments of the present invention include a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on the channel layer. A first ohmic contact is provided on the barrier layer-to provide a source electrode and a second ohmic contact is also provided on the barrier layer and is spaced apart from the source electrode to provide a drain electrode. A GaN-based cap segment is provided on the barrier layer between the source electrode and the drain electrode. The GaN-based cap segment has a first sidewall adjacent and spaced apart from the source electrode and may have a second sidewall adjacent and spaced apart from the drain electrode. A non-ohmic contact is provided on the GaN-based cap segment to provide a gate contact. The gate contact has a first sidewall which is substantially aligned with the first sidewall of the GaN-based cap segment.