Abstract: A comparator used in an enhanced N-WELL pad voltage tracking circuit for high (5 Volts) voltage-tolerant buffers is designed to eliminate current leakage when the input/output is tristated and is being driven externally by a weak voltage source. This is accomplished by comparing the pad voltage supplied from the external source to a reference voltage that is a predetermined amount (VTP) less than the low internal voltage source (VDD). Thus, switchover for tracking of the N-WELL voltage tracks very closely the voltage VDD, reducing the differential voltage between the N-WELL and the pad on the pull-up driver for the system, thereby keeping the driver off and eliminating leakage current. The reference voltage is generated either by a diode voltage drop or by a weak source follower.

Abstract: A computational circuit which has a capacitive coupling for weighted addition. Addition is performed by the capacitive coupling. By connecting and disconnecting capacitances of the capacitive coupling, multiplication can be executed by changing the weights of the capacitors. An inverter with a feed back capacitance is connected to a computational circuit to improve the accuracy of the computation.Capacitances consist of unit capacitances of scattered distribution, so that the deviation of the capacities is minimized.

Abstract: A flip-flop circuit that includes a first NAND gate (11) responsive to a D input to the flip-flop circuit and a first mode control signal for providing a first NAND gate output; a second NAND gate (12) responsive to a serial scan input to the flip-flop circuit and a second mode control signal for providing a second NAND gate output; an inverter (21) responsive to the first NAND gate output for providing an inverter output; a first transmission gate responsive to the first NAND gate output and the second NAND gate output for providing a first transmission gate output, the first transmission gate output being a replica of the inverter output when the first mode control signal is of a first logical state and the second mode control signal is of a second logical state, and the first transmission gate output being of high impedance when the first mode control signal is of the second logical state and the second mode control signal is of the first logical state; a second transmission gate (32) responsive to the fir

Abstract: A polarizing element or polarizing plate comprising a layer having photoactive molecules and a layer containing dichroic molecules formed in contact with said layer, which can easily be produced without a stretching procedure so as to have a complicated pattern, a curved surface or a large area; and a process for producing said polarizing element or polarizing plate which is characterized by irradiating a layer having photoactive molecules on a substrate with linear polarized light, and then forming a dichroic molecular layer on the irradiated layer.

Abstract: The present invention provides a method and apparatus for detecting voltage drops on an IC chip. The device operates by using a reference voltage to detect the voltage range of a local voltage. A multiple number of reference voltages are used (or predetermined) between the reference voltage and the ground voltage. The voltage drop detecting device includes a multiple number of inverters having to the local voltage as its input. The inverters each have a trigger voltage corresponding to one of the reference positions. When the local voltage is smaller than the trigger voltage of the inverter, a low to high voltage switching is present at the output. A multiple number of positive-edge triggering devices, coupled to the reference voltage as one of its inputs, are each coupled to one of the inverters. A corresponding inverter presents a low to high switching to make the reference voltage present at the corresponding output terminal. The voltage range of the local voltage is detected at the output terminals.

Abstract: A timing generator which receives a rate signal and generates an output signal based on the rate signal, and comprises at least two delay lines for causing delays in the rate signal, a formatter for receiving signals from the delay lines and for determining the rise and fall of an output signal according to such signals from the delay lines, and for generating an output signal, memories for storing delay time data from the delay lines, and a data selector for taking the delay time data from the memories and to switch the delay time data, whereby accurate timing signals are generated utilizing short skew adjustment time.

Abstract: A charge pump circuit has a first transistor connected to a first power source and having a control electrode to receive a first control signal; a second transistor connected to a second power source and having a control electrode to receive a second control signal; a third transistor and a current source connected in series between the first and second transistors, a node between the third transistor and the current source providing a signal, which is passed through a low-pass filter to provide a VCO input signal; and a control voltage generator for generating a control voltage according to the VCO input signal and applying the control voltage to a control electrode of the third transistor. This charge pump circuit realizes a stable PLL operation for a wide range of VCO input voltages, has little data rate dependency, and operates at high speed.

Abstract: Several users emit their own selection signal and clock signal to their respective selection circuits. The selection circuits send selection criteria to all other selection circuits and the clock switching stage. The selection circuit sends an activity signal to a digital circuit based on the allocated user's selection signal, the selection criteria of all the other selection circuits and the selected clock signal.

Abstract: A semiconductor integrated circuit includes a chip having an element forming surface with a side thereof extending along a first direction, an output buffer portion provided on the element forming surface of the chip, a plurality of output transistors having different emitter areas provided on the element forming surface of the chip and arranged approximately in a line along a second direction, which is perpendicular to the first direction, and a pad provided on the element forming surface of the chip. An output circuit is formed by the output buffer portion, a portion or all of the output transistors and the pad. The output buffer portion, the output transistors and the pad are arranged approximately in a line along the second direction.

Abstract: A programmable analog array (10) comprises an array of configurable cells (11), each cell (11) including analog circuitry (12) and digital circuitry (14). The cells (11) are configured for a particular functional application. The digital circuitry (14) converts an analog signal generated by the analog circuitry (12) into digital control information, which is then used to adjust the analog circuitry (12). Therefore, the analog circuitry (12) and the digital circuitry (14) form a digital feedback loop. The digital feedback loop is established either within a single cell or among neighboring cells. Thus, the digital feedback loop is established without using a global data bus.

Abstract: A circuit for synchronizing a multiplied system clock signal includes a device for generating a system clock signal, a first device that receives the system clock signal and generates a synchronization signal and at least one second device that receives the system clock signal and the synchronization signal. Each of the second devices includes a device for multiplying the system clock signal to produce the multiplied system clock signal and a device for synchronizing the multiplied system clock signal with each other multiplied system clock signal produced by the other second devices based on the synchronization signal.

Abstract: Clock skew is minimized in an ASIC by grid-partitioning the IC chip into a number of preferably equal sized regions. An on-chip clock or buffer unit provides a clock signal to be distributed to buffers and clocked loads also on the IC. Equal length metal interconnect traces are formed in a preferably "H"-shaped configuration such that the termini and the center of the traces overlie buffer regions that will receive the distributed clock signal. Metallization interconnect paths are dictated by placement of joiner cells. By making each metal interconnect trace equal in overall length and in layer sub-lengths (if multiple metallization layers are present), clock skew along the interconnect traces is minimized macroscopically. A series of prioritized net lists is generated, defining interconnect paths to each region. A buffer is centrally located within each region, and is surrounded by a ring containing clocked loads to be coupled to the clock signal.

Abstract: In a circuit provided in a single integrated circuit unit for use in a signal delay device, there is provided with a device in which an input signal is delayed and a plurality of delay signals, each having a different delay period from the input signal, are outputted, and a detector in which a delay signal having a specific relation with the input signal among the plurality of delay signals is detected.

Abstract: A clock signal generator can prevent unnecessary power consumption and can lower the power consumption of a system or a chip as a whole. A clock generator has a plurality of multipliers having variable multiplying factors and multiplying a single input reference clock signal by a designated multiplying factor. A plurality of frequency dividers have variable divide factors and divide a clock signal by a designated dividing factor. A clock selector selects a clock signal which has a required frequency according to a status signal STS from each of the functional locks from among the clock signals having a plurality of frequencies generated by the clock generator. The clock selectors stops the operation of the multipliers or the frequency dividers which are generating unused frequencies by switching clock signals.

Abstract: A CMOS differential transmitter and matched receiver apparatus and method for transmitting data. The system uses a CMOS bias network to create low voltage swings and optimize the voltage offsets to compensate for variations caused by the manufacturing process, and thereby increase data transmission rates to approximately 1 gigabit per second.

Abstract: The phase locked loop (PLL) control apparatus includes a selector which selects input signals, for an active system and a standby system having a clock signal and a frame pulse signal synchronized with the clock signal, by means of a line switching signal. The phase difference between the frame pulses before and after the line switching is output by a frame pulse phase comparator. On the other hand, accompanying the line switching, a frequency divided clock output from a frequency divider is branched in a PLL control circuit which carries out the phase matching of the clocks. The branched clock is converted to pseudo clocks with duty factors larger than and smaller than 50% by a duty factor controller. A clock selector which selects one out of the frequency divided clock and the pseudo clock in response to the phase difference of the frame pulses is installed between a clock phase comparator and a low-pass filter of the PLL control circuit.

Abstract: A controlled capacitor system, which includes a capacitor element (C1) and a forward-biased diode element (D2) connected in series with the capacitor element (C1). The system is such that the diode element (D2) has a capacitance which is less than the capacitance of the capacitance of the capacitor element (C1) when the diode element (D2) is under zero bias. The capacitance of the diode element (D2) is controlled by varying the forward current (I2) through the diode (D2). The forward current (I2) acting to control the capacitance of the diode element is selected such that the capacitance of the diode element (D2) is smaller than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) is below a minimum value. The capacitance of the diode element (D2) is bigger than the capacitance of the capacitor element (C1) when the current (I2) through the diode element (D2) exceeds a maximum value.

Abstract: An edge-trigger pulse generator that is suitable for use in a signal generator is disclosed, including positive and negative logic embodiments. The positive logic embodiment includes: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; a NAND gate for receiving outputs of the first time-delay circuit and the second time-delay circuit, and performing a NAND logical operation for the outputs; and an inverter for receiving and inverting output of the NAND gate, so that the width of an pulse output from the edge-trigger pulse generator can be determined merely by the edge-trigger pulse generator while the width of the input pulse is not wider than a predetermined width. The negative logic embodiment replaces the NAND gate with NOR gate and has a second time-delay circuit that is different from the second time-delay circuit of the first embodiment.

Abstract: A clock signal distribution circuit provides a synchronized clock signal to a plurality of chips implementing an integrated circuit. The clock signal distribution circuit has a first and a second phase lock loop, a series of voltage controlled delay circuits and a pair of transmission lines formed between the chips. The input clock signal is transmitted from the first chip to the second chip through a transmission line, the end of which is a node supplying the output clock signal to the internal circuit of the second chip. The clock signal is then returned from the output node through the second transmission line. The first phase lock loop controls the series of voltage controlled delay circuits such that the signal at a midpoint reference node has a phase equal to the phase of the output clock signal. The second phase lock loop controls the first voltage controlled delay circuit such that the signal at the first output node has a phase synchronized with the phase of the input clock signal.

Abstract: A variable delay circuit includes a gate chain of first to n-th delay gates (n is an integer larger than 2) connected in series to each other via delay gate wirings having respective wiring lengths, the first delay gate receiving an input signal for delay; first to n-th separator gates to which the outputs of the first to n-th delay gates are input, respectively; first to n-th separator gate wirings having wiring lengths successively shortened from the first to n-th separator gate, first ends respectively connected to the first to n-th separator gates, and second ends connected to an n:1 selector, for selecting one of the outputs of the first to n-th separator gates in according with a select signal, and a select signal generating circuit for controlling the n:1 selector. The variable delay circuit has no loss of resolution due to parasitic capacitance of the delay gate wirings.