Abstract: A globally distributed system clock is received and selectively gated by local clock generators responsive to global control signals. The local clock generators, which are located proximately to sequential circuits having serial scan paths, produce scan and functional clock signals adapted to the sequential circuits, which may have a variety of required timing diagrams.

Abstract: An FET with a lightly doped drain is connected between an input/output pad and ground and is protected from ESD at a pad by a structure that includes a resistor formed by the process step for the lightly doped drain. The resistor adjoins and interconnects a diffusion underlying the pad and the diffusion for the drain of the FET. A parasitic bipolar transistor is formed by the pad diffusion, the source diffusion for the FET, and the intervening substrate. When an ESD voltage appears at the pad, the FET conducts in circuit with the resistor and the voltage drop across the resistor helps to protect the FET and to turn on this parasitic bipolar transistor (in preference to a parasitic bipolar transistor otherwise formed by the FET) and thereby hold down the ESD voltage at the pad and at the drain of the FET. The FET and resistor can be formed as a number of parallel connected FETs and resistors located symmetrically on opposite sides of the pad diffusion. Protection for an input inverter circuit is also provided.

Abstract: A time-continuous tunable Gm-C integrator including a "super Gm" differential input stage (O1; MI1/O2, MI2) and using linear and constant degeneration resistors (R1/R2) for obtaining the most optimal linear input-voltage to output-current conversion is tunable in a time-continuous manner. The integrator is provided with three tuning CMOS transistors (MU1, MU2, MU3) controlling the integrating currents flowing between the input stages and from the input stages towards the outputs (OP/ON). By a suitable control of the tuning transistors and owing to the fact that the voltage swing across the latter is small, it is possible to obtain a perfectly linear transconductance (Gm) characteristic over the whole operating range of the integrator.

Abstract: Controlled delay digital clock signal generator, characterised in that it comprises means (I5, I6, I7, I8, I9, I10, IT7, IT8, IT9, IT10, C4) to generate from a clock signal (CK) and its complementary signal (CKB) a ramp signal comprising at least two segments of positive slope and at least two segments of negative slope, means (I1, I2, IT1, IT2, IT3, C2, CET1T2, AMPLI, I3, I4, IT4, IT5, IT6, C3, CET3T4, AMPL2) for separate control of the slopes of the said segments, means with trigger circuits (AMPLO) for converting the ramp signal (RAMP) into a square signal (CKQ) means (NO0, A0, A1, NO1) for achieving the logic combinations of the delayed square clock signal (CKQ) resulting from the conversion with the clock signal (CK) and the clock complementary clock signal (CKB) of the said clock signal to obtain as many delayed digital clock signals as the ramp signal has segments of different slopes.

Abstract: A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initialization, the logic circuit's input signal line is recoupled for normal operation.

Abstract: A high efficiency charge pump for low and wide voltage ranges. The charge pump includes main and secondary charge pumps, the secondary charge pump is employed to avoid the Vt.sub.N drop that the main charge pump exhibits. The secondary charge pump allows the main charge pump to pump to a theoretical maximum of 2 VCC, while maintaining an efficiency close to 40%.

Abstract: A power control circuit for an electronic equipment capable of turning off a power switch to prevent useless consumption of a power supply battery when non-operation of an electronic equipment over a predetermined period of time is detected. A counter circuit 25 is reset when a power switch is turned on, so that a main switch is turned on to render an electronic equipment operative. When a signal is generated from a logical circuit detecting auto cut-off conditions, a clock signal is fed from a control circuit to the counter circuit, so that the main switch is turned off by a carryover signal. After the auto cut-off conditions are detected, a predetermined number of clock pulses are counted to cause the main switch to be turned off, to thereby prevent malfunction of the electronic equipment due to incidental introduction of noise thereinto.

Abstract: In a noise canceler, a pilot-canceling signal without noise is applied to the inverting input of a subtracter via a first MOS transistor. When a noise signal is present, a pilot signal and noise signal passing through a capacitor are applied to the inverting input port of the subtracter via a second MOS transistor to cancel the noise signal contained in the composite input signal. In the canceler, external noise may be digitally converted and the inverted noise thereof stored in a memory. When a noise signal detector detects the external noise, inverted data corresponding to the external noise is output from the memory. The detector enables an address generator to continuously generate addresses. The memory reads out inverted noise patterns which are converted into analog form and transmitted via a speaker, thereby canceling noises produced by various electrical and electronic appliances as well as nearby automobiles and aircraft.

Abstract: A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such that the latter signals are substantially synchronous with the processor clock signals. D-flip-flop circuitry together with a delay unit having an adjustable time delay are used to generate a gated clock signal. The overall time delay, from the time of which the circuitry is enabled until the gated clock signal is produced, is appropriately set by selecting the required time delay so that the overall time delay is essentially the same as the time delay required to generate the processor clock signals. Accordingly, the edges of the gated clock signals can be made to coincide with the edges of the processor clock signals.

Abstract: A method and apparatus for transitioning between power supply levels. In one form, the present invention uses a circuit (22) in a data processing system (10) to smoothly and gradually transition a Power Output signal from a first power supply level to a second power supply level during operation. This transition from a first power supply level to a second power supply level must be smooth and gradual so that a circuit, such as oscillator circuit (12), which is receiving its power from Power Output, may continue to function properly during the transition. A Control signal, which can change back and forth between a first logic level and a second logic level, is used to select which power supply level will be provided as the Power Output.

Abstract: In a tone control circuit of luminance signals, an adjusting current is used to add to or subtract from input signals with a gain control. Output signals are thus controlled to have a predetermined gradient based on an arbitrary output setting voltage against the input signals, and an input-output characteristic represented by an arbitrary line graph is obtained by plural gradient adjusting circuits.

Abstract: A fully differential switched-capacitor biquad low pass filter (40) includes a first stage (54), second stage (56), common-mode circuits (55, 72), and feedback transmission gates (73, 74). The first stage (54) includes a first operational amplifier (47), and the second stage (56) includes a second operational amplifier (69). Glitches, or transients, which are caused by the operational amplifiers (47, 69) operating in slew rate limit mode, are prevented from affecting the differential output signals of the filter (40) when the filter (40) is operating with a continuous time output. This is accomplished by preventing the operational amplifiers (47, 69) from operating in slew rate limit mode, or by adjusting the clock signals such that the output of the filter (40) is not coupled to an operational amplifier (47, 69) that is recovering from operation in slew rate limit mode.

Abstract: An integrating circuit is formed in the present invention, of which the active element is a pair of bipolar transistors (T5/T6) or a CMOS transistor (T8) which with the aid of switches (s81 to s88) controls the storing of a sample charge from the signal voltage (Us) in a sampling capacitor (Ci) and the discharging of the sample into an integrating capacitor (Co). The circuit only consumes current while charges are being transferred.

Abstract: A signal processing circuit is to be connected to an output stage of a charge-coupled device which includes a reference signal circuit and a CCD signal circuit that generate first and second output signals, respectively. The signal processing circuit includes a differential circuit and first and second amplifiers. The differential circuit receives the first and second output signals from the output stage of the charge-coupled device and generates a first signal corresponding to the first output signal and a second signal corresponding to the second output signal. The first amplifier has an output, a first input which receives the first signal from the differential circuit, and a second input which is connected to the output to serve as a negative feedback input thereto. The second amplifier has an output, a first input which receives the second signal from the differential circuit, and a second input which is connected to the output of the first amplifier to serve as a negative feedback input thereto.

Abstract: A control apparatus which includes apparatus for storing a first digital code, apparatus for storing a second digital code, and apparatus for comparing the first and second digital codes, the apparatus for comparing including first and second generally dish shaped members that are dimensioned and configured for nesting relationship. In some forms of the invention the dish shaped members are each rotationally symmetrical. The first and second dish shaped members may each include a plurality of steps on the face thereof. At least one of the first and second dish shaped members includes a plurality of steps on the face thereof. The other of said first and second dish shaped members may includes a plurality of steps on the face thereof. The apparatus will often include means for conducting disposed respectively in contact with the conductive generally planar members. Some of the generally planar members may have tab portions for connection thereto.

Abstract: A programmable hold-off circuit for an integrated circuit for selectively providing hold-off for outputs of the integrated circuit. The programmable hold-off circuit includes a hold-off latch for receiving an output signal from the interior logic of the integrated circuit, and for providing a hold-off latch output, an output buffer responsive to hold-off latch output for providing a buffered output, a hold-off control circuit responsive to a hold clock for controlling the hold-off latch to be continuously transparent when the hold-off control circuit is programmed for no hold-off, and for controlling the hold-off latch pursuant to the hold clock when the hold-off control circuit is programmed for hold-off. The hold-off control circuit is programmed, for example, pursuant to a boundary scan flip-flop.

Abstract: A clipper includes an amplifier having a non-inverting input node, an inverting input node, and an output node. A feedback transistor has its base connected to the amplifier output node and its collector connected to the non-inverting input node for providing unilaterally conductive degenerative current feedback between the output node and the non-inverting input node. A resistor is connected between the non-inverting input node and an input terminal for conducting a current supplied via the collector-to-emitter path of the feedback transistor which is proportional to the amplitude of an unclipped portion of the signal applied between the input terminal and the inverting input node. When a reference potential is applied to the inverting input node and an AC input signal varying about the reference potential is applied to the input terminal, the stage functions as a negative half-wave rectifier.

Abstract: In accordance with the present invention, the above and other objects and advantages are obtained with a bootstrap circuit for a power MOS transistor in a high side configuration. Such circuit includes a first capacitor chargeable to a first voltage which is a function of the supply voltage of the power transistor. It further includes a second capacitor combined with the first capacitor so as to provide a second voltage which is higher than the first voltage and the threshold voltage of the power transistor.

Abstract: A filter circuit comprises a glass delay line for giving a predetermined amount of delay to an input signal, and an active filter connected to the glass delay line for performing an impedance matching for the glass delay line. By changing the transconductance g.sub.m of differential amplifiers which constitute the active filter, the amount of delay of the glass delay line can be adjusted.

Abstract: A circuit having a first integrator 46 and a sensor 20 for sensing a difference between an output voltage of the first integrator and a trip voltage provides a signal indicative of whether the output voltage is greater than the trip voltage. Resetting circuitry 40, 42 and 44 is coupled to the sensor 20 for softly bringing the output voltage lower than the trip voltage when the signal from the sensor 20 indicates that the output voltage is greater than the trip voltage.