Abstract: The complementary multiplexer includes a first pass-gate, formed from a single PMOS transistor, and a second pass-gate formed from a single NMOS transistor. The gates of the PMOS and NMOS transistors are connected directly to a select input line. No inversion of the select input signal is required. A compensation circuit is connected to outputs of the pass-gates for compensating any voltage differences between signals received through the first pass-gate as opposed to those received through the second pass-gate. Full CMOS and bi-CMOS implementations are described herein. An exclusive OR-gate circuit, incorporating a bi-CMOS implementation of the multiplexer, is also described herein.

Abstract: A circuit combining the functions of phase-sensitive rectifier and integrator uses an operational amplifier and capacitors. A control signal switches a capacitor in and out of a feedback loop containing a second feedback capacitor, resulting in a residual charge in the second feedback capacitor if there is a phase-difference between an input signal and the control signal. The invention may also incorporate an automatic offset compensation circuit by using additional switches and a second control signal. The capacitor that is switched in and out of the feedback loop is coupled to a compensation capacitor during periods when the capacitor is not being used for the phase-sensitive rectifier and integrator portions of the circuit. The circuit arrangement allows the use of long time constants in the integrator portion of the circuit.

Abstract: A bus driver circuit for applying a binary signal to a bus line comprises an input transistor (Q.sub.1) for receiving the signal to be applied to the bus line and an output transistor (Q.sub.2) which taps the signal from the emitter of the input transistor and furnishes its output signal at its collector via a Schottky diode (D.sub.1). Between the base and the collector of the output transistor (Q.sub.2) the collector-emitter path of a transistor (Q.sub.3) is inserted, to the base of which a reference voltage (U.sub.ref) for defining the low value (L) of the binary signal to be applied to the bus line is applied via a Schottky diode (D.sub.3).

Abstract: A programmable counter composed of D-type flipflops receives a clock pulse having a constant frequency and is configured to generate a count pulse when a count value reaches a programmed number. A ring counter composed of D-type flipflops receives the count pulse from the programmable counter. A coincidence detection and control circuit detects a predetermined count value of the ring counter, and modifies the programmed maximum count number of the programmable counter, so that the maximum count value of the programmable counter can be selected from either an ordinary maximum count number or the predetermined maximum count number.

Abstract: A digital clock circuit generates a high-speed clock and window pulses substantially centered about transitions of the high-speed clock in one quadrant of an integrated circuit (IC) and routes the high-speed clock and window pulses to other quadrants of the IC where a low-speed clock generator develops a low-speed clock signal from the window pulses. A control circuit checks alignment between the high-speed and low-speed clock signals and adjusts first and second shift registers to control the delay in generating the low-speed clock as necessary to maintain alignment. The first shift register controls the falling edge of the low-speed clock signal and the second shift register controls the rising edge of the low-speed clock signal.

Abstract: A MOS hysteresis comparator having a source transistor bias circuit which generates a source current Is that compensates for temperature and manufacturing process variations, thereby providing a hysteresis characteristic which is substantially insensitive to such temperature and manufacturing process variations. The source transistor bias circuit includes a set of MOS transistors which replicate the comparator load currents which occur at the switch points of the comparator, and a source transistor which mirrors the sum of the replicated currents to form the source current Is of the comparator.

Abstract: This invention is an improved pull-up circuit for P-channel sense amplifiers in dynamic random access memory arrays having non-bootstrapped wordlines. The improved pull-up circuit features a voltage-comparator-controlled P-channel device which couples the power supply bus to a pull-up node for high current flow to the node and to digit lines which are coupled to the node via P-channel isolation devices. During the pull-up cycle, the P-channel device remains "on" as long as a reference voltage is greater than a variable voltage which represents the voltage level on portions of the digit lines farthest from the P-channel sense amplifier. The pull-up circuit also has an N-channel device which couples the power supply node to the pull-up node for maintenance of a desired voltage level equal to V.sub.cc minus the threshold voltage of the N-channel device.

Abstract: A current source is selectively switched into the output circuit of a differential amplifier for producing hysteresis. In a circuit embodying the invention, a differential amplifier (diff-amp) stage operated at a first current level set by a first current source has first and second input terminals for the application therebetween of a differential input signal and first and second output nodes for the production of differential output signals. A second current source for inducing hysteresis is connected to one of the output nodes of the diff-amp and is selectively enabled. A differential input signal (VIN) is applied across the input terminals. When VIN varies in one direction and reaches a first threshold level, the second, hysteresis inducing, current source is enabled whereby a larger current can flow in the one node. VIN then has to vary in the opposite direction and reach a second threshold level to disable the second current source.

Abstract: In a switching circuit comprising an output field effect transistor having an output drain electrode connected to a power supply through a load resistor and an output gate electrode supplied with an input voltage, a reference field effect transistor has a reference drain electrode connected to the power supply through a reference resistor and a reference gate electrode supplied with the input voltage. Each of the output and the reference field effect transistors is made of a metal oxide semiconductor. A comparator has a load input terminal connected to a load node of the output drain electrode and the load resistor and a reference input terminal connected to a reference node of the reference drain electrode and the reference resistor. The comparator compares a load sensing voltage from the load node with a reference voltage from the reference node to produce a compare output voltage when the load sensing voltage is higher than the reference voltage.

Abstract: An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.

Abstract: There is disclosed a circuit arrangement to permit reduction of the occupation area and the power consumption in a complementary logic circuit constituting a sequence circuit such that it is used in a manner switched between ON state and OFF state. This circuit arrangement as a sequence circuit comprises a delay circuit 2 comprised of a group of D flip-flops of the dynamic type and a combination circuit 1 connected to the delay circuit, thus to allow all inputs of the combination circuit 1 to be compulsorily brought into a predetermined state during an operation stop period of the delay circuit by an input control circuit 3, and to allow the delay circuit to be placed in a data through condition, with each of master and slave latches of the group of flip-flops constituting the delay circuit being caused to be inoperative or inactive, by an operation stop control circuit 4.

Abstract: A first power FET has a source terminal, a gate terminal and a drain terminal and a load is connected in series with the source terminal of the power FET. A circuit configuration for triggering the first power FET includes a first input terminal. A first diode and a capacitor are connected between the first input terminal and the gate terminal of the first power FET. A second FET of the opposite channel type from that of the first power FET has a gate terminal and has drain and source terminals defining a drain-to-source path. A second diode is connected between the first diode and the capacitor and is connected through the drain-to-source path of the second FET to the drain terminal of the power FET. A resistor is connected between the gate and source terminals of the second FET. A controllable switch is connected to the gate terminal of the second FET. A second input terminal is connected to the controllable switch for receiving a voltage being lower than a supply voltage.

Abstract: A binary threshold value setting circuit comprises: a first detecting section to detect the positive polarity side of an input signal, a second detecting section to detect the negative polarity side of the signal; a first envelope detecting section to perform an envelope detection to the signal detected by the first detecting section, a second envelope detecting section to perform an envelope detection to the signal detected by the second detecting section, a threshold value setting section to generate a signal at a level between the level of the signal which has been envelope detected by the first envelope detecting section and the level of the signal which has been envelope detected by the second envelope detecting section, and a capacitor connected between the output side of the first detecting section and the output side of the second detecting section.

Abstract: An attenuator circuit uses single point control to adjust the attenuation levels between first and second nodes. The attenuator is set-up as a .pi.-network with a pass transistor and first and second shunt transistors. Capacitors are coupled in the drain and source conduction paths of the first and second shunt transistors for DC isolation to float the shunt transistors. A control voltage applied at the drain of the pass transistor and the gates of the first and second shunt transistors controls the attenuation level. A parallel resistor and capacitor combination at the drain of the first shunt transistor provides tuning to match the input impedance of the attenuator to the sourcing circuit.

Abstract: The invention relates to method and apparatus for adjusting a clock signal which is supplied to an electronic apparatus. After the turn-on of a power source of the electronic apparatus, it is detected that a temperature of at least a part of devices in the electronic apparatus substantially reaches a saturation state. When the temperature of the device reaches the saturation state, a phase adjustment of the clock signal of the electronic apparatus is executed. After completion of the phase adjustment of the clock signal, its adjusting state is fixed.