Abstract: A semiconductor device including: a first silicon level including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon level; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, disposed over the third metal layer; a third level including a plurality of third transistors, disposed over the second level; a via disposed through the second and third levels; a fourth metal layer disposed over the third level; a fifth metal layer disposed over the fourth metal layer; and a fourth level including a second single crystal silicon layer and is disposed over the fifth metal layer, where each of the plurality of second transistors includes a metal gate, and the via has a diameter of less than 450 nm.

Abstract: A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.

Abstract: A flexible display panel and a flexible array substrate are provided. The flexible display panel includes a flexible base and a thin film transistor. The thin film transistor includes an active layer, and the active layer is arranged on the flexible base. Open pores are formed in the active layer. The open pores penetrate through at least one part of the active layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanostructures formed over a substrate, and a first S/D structure formed on sidewall surfaces of the first semiconductor nanostructures. The semiconductor device includes a plurality of second semiconductor nanostructures formed over the substrate, and a second S/D structure formed on sidewall surfaces of the second semiconductor nanostructures. The semiconductor device includes an isolation structure formed between the first S/D structure and the second S/D structure, and the isolation structure has a first sidewall surface in direct contact with the first S/D structure and a second sidewall surface in direct contact with the second S/D structure.

Abstract: A nitride semiconductor light emitting element includes: n-side and p-side nitride semiconductor layers; and an active layer. The active layer includes a plurality of well layers and a plurality of barrier layers. The plurality of well layers include first well layers, and second well layers positioned closer to the p-side nitride semiconductor layer than the first well layers. At least one of the plurality of barrier layers positioned between the first well layers and at least one of the plurality of barrier layers positioned between the second well layers respectively include a first barrier layer containing an n-type impurity, and a second barrier layer, wherein a concentration of the n-type impurity in the second barrier layer is lower than a concentration of the n-type impurity in the first barrier layer, and wherein the second barrier layer is positioned closer to the p-side nitride semiconductor layer than the first barrier layer.

Abstract: A semiconductor device including a substrate; gate structures spaced apart from each other on the substrate, each gate structure including a gate electrode and a gate capping pattern; source/drain patterns on opposite sides of the gate structures; first isolation patterns that respectively penetrate adjacent gate structures; and a second isolation pattern that extends between adjacent source/drain patterns, and penetrates at least one gate structure, wherein each first isolation pattern separates the gate structures such that the gate structures are spaced apart from each other, the first isolation patterns are aligned with each other, and top surfaces of the first and second isolation patterns are each located at a level the same as or higher than a level of a top surface of the gate capping pattern.

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a gate dielectric layer over a fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer. The method further includes forming a first dielectric layer formed over the gate dielectric layer. In addition, the method includes forming a first conductive layer on the gate dielectric layer. A bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer.

Abstract: A display panel and a display device are provided. The display panel includes: a sub-pixel including a pixel circuit and a light-emitting element, the light-emitting element including a first electrode; a first insulating layer, the first electrode being connected with the pixel circuit through a first via hole penetrating the first insulating layer; a pixel definition layer including an opening; the first electrode includes a main body portion and a connecting portion, the main body portion is at least partially overlapped with the opening, the connecting portion is at least partially overlapped with the first via hole, a size of the connecting portion at the first via hole in a first direction is ? to ? of a size of the main body portion in the first direction.

Abstract: A display panel and a display device are provided. The display panel comprises a substrate, a source and drain metal layer, a first planarization layer, an auxiliary metal layer, a second planarization layer, an anode and a light emitting pixel. The anode comprises a first anode part corresponding to the light emitting pixel. By removing the auxiliary metal layer directly below the first anode part, the orthographic projection of the auxiliary metal layer on the substrate is outside the orthographic projection of the first anode part on the substrate, which helps to eliminate horizontal diffraction fringes.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a pixel circuit, and the pixel circuit includes a light-emitting element, a driving circuit and a capacitor circuit. The driving circuit is configured to drive the light-emitting element to emit light; a first terminal of the capacitor circuit is electrically connected to a control terminal of the driving circuit, and a second terminal of the capacitor circuit is electrically connected to a data writing-in node; the capacitor circuit includes at least two capacitors connected in parallel with each other.

Abstract: A display panel includes a substrate; and a thin film transistor (TFT) array layer disposed on the substrate, the TFT array layer being provided with a first TFT, a plurality of second TFTs, and a storage capacitor arranged at intervals therein; wherein the first TFT comprises a polysilicon semiconductor layer and a first gate electrode laminated on each other, each of the second TFTs comprises an oxide semiconductor layer and a second gate electrode laminated on each other, the storage capacitor comprises a first polar plate and a second polar plate opposite to each other, the first polar plate is disposed in a same layer and comprises a same material as the first gate electrode, and the second polar plate is disposed in a same layer and comprises a same material as the second gate electrode.

Abstract: A transparent display device is disclosed, which may have high light transmittance in a non-display area as well as a display area, and may increase or maximize a light emission area in a non-transmissive area. The transparent display device comprises a substrate provided with a display area, in which a plurality of subpixels are disposed, and a non-display area adjacent to the display area, anode electrodes provided in each of the plurality of subpixels over the substrate, a light emitting layer provided over the anode electrodes, a cathode electrode provided over the light emitting layer, a pixel power line provided over the substrate and extended in the display area in a first direction, and a common power line provided over the substrate and extended in the display area in the first direction. The display area includes a non-transmissive area provided with the common power line and the pixel power line, and a transmissive area provided between the common power line and the pixel power line.

Abstract: A micro-light emitting diode (micro-LED) device includes semiconductor mesa structures, and waveguides and grating couplers in regions of a semiconductor layer between the semiconductor mesa structures. At least some light emitted in the active region of each semiconductor mesa structure can be coupled into and guided by a waveguide towards a grating coupler. The grating coupler is configured to diffract the guided light out of the micro-LED device, for example, in a direction substantially perpendicular to the light-emitting surface of the micro-LED device, through regions between the semiconductor mesa structures.

Abstract: An organic light-emitting display apparatus includes: a display unit including an organic light-emitting element, a driving transistor electrically connected to the organic light-emitting element, and a capacitor; and a pad unit connected to the display unit, the capacitor including: a first conductive layer disposed on a substrate; a second conductive layer interposed between the substrate facing a first surface of the first conductive layer; and a third conductive layer disposed facing a second surface of the first conductive layer opposing the first surface of the first conductive layer, the third conductive layer being electrically connected to the second conductive layer.

Abstract: A light emitter mounting board for improving light extraction efficiency includes an insulating substrate, an electrode layer, a resin layer, a coating layer, and a reflective electrode. The resin layer is located on the electrode layer and has a through-hole portion extending in a thickness direction. The coating layer covers a surface of the resin layer and an inner peripheral surface of the through-hole portion. The coating layer includes an in-hole portion covering the inner peripheral surface and having a lateral thickness gradually increasing from the surface of the resin layer toward the electrode layer. The reflective electrode extends at least on a surface of the in-hole portion of the coating layer and on an exposed portion of a surface of the electrode layer.

Abstract: A pixel driving circuit includes a first thin film transistor having a double-gate structure, a conductive layer and a second thin film transistor. The first thin film transistor includes a first active layer. The first active layer includes a first and second semiconductor portions and a conductor portion located therebetween. The conductor portion has a first doping concentration. The conductive layer is at least partially opposite to the conductor portion, so that the conductive layer and the conductor portion form a capacitor. The conductive layer is configured to electrically connect to an initial voltage terminal. The second thin film transistor includes a second active layer and a first gate. A portion of the second active layer directly opposite to the first gate has a second doping concentration, and the second doping concentration is lower than the first doping concentration.

Abstract: A magnetic memory device including a first memory cell which includes a first stacked structure including a magnetic layer and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer. Each of the first stacked structure and the second stacked structure includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer. A concentration of iron (Fe) contained in the first magnetic layer included in the first stacked structure and a concentration of iron (Fe) contained in the first magnetic layer included in the second stacked structure are different from each other.

Abstract: The present application provides a display panel and a display device, the display panel includes a transistor located in a display region, the transistor is at least one of a main transistor, an auxiliary transistor, and a voltage divider transistor. The transistor includes a channel located above a semiconductor layer and a source electrode and a drain electrode located on an electrode layer. The drain electrode includes a drain electrode tip region, and an orthographic projection of the drain electrode tip region on the semiconductor layer is located outside the channel.

Abstract: A display device having a plurality of pixel structures, each of the plurality of the pixel structures including: a substrate; a first active pattern on the substrate; a first gate line on the first active pattern and extending in a first direction; a first connecting pattern on the first gate line and configured to transmit an initialization voltage; a second connecting pattern on the first connecting pattern and electrically connected to the first active pattern and the first connecting pattern; and a first electrode on the second connecting pattern and configured to be initialized in response to the initialization voltage.

Abstract: The display apparatus includes a substrate, a first active layer disposed on the substrate, a first gate layer disposed on a layer covering the first active layer, the first gate layer including a first gate electrode, a second gate layer disposed on a layer covering the first gate layer, the second gate layer including an initialization line including a first part of a second electrode; a second active layer disposed on a layer covering the second gate layer, the second active layer including a second active region overlapping the first part of the second electrode; a third gate layer disposed on a layer covering the second active layer, the third gate layer including a second part of the second electrode overlapping the second active region; and a first source/drain layer disposed on a layer covering the third gate layer, the first source/drain layer including a first connection line.