Patents Examined by Tan N. Tran
  • Patent number: 10317104
    Abstract: Apparatus, systems, methods, and related computer program products for optimizing a schedule of setpoint temperatures used in the control of an HVAC system. The systems disclosed include an energy management system in operation with an intelligent, network-connected thermostat located at a structure. The thermostat includes a schedule of setpoint temperatures that is used to control an HVAC system associated with a structure in which the thermostat is located. The schedule of setpoint temperatures is continually adjusted by small, unnoticeable amounts so that the schedule migrates from the original schedule to an optimal schedule. The optimal schedule may be optimal in terms of energy consumption or some other terms.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 11, 2019
    Assignee: Google LLC
    Inventors: Yoky Matsuoka, Mark Malhotra, Evan Fisher
  • Patent number: 10319885
    Abstract: The disclosure provides a display device and a LED emitting light on four sides thereof. The LED emitting light on four sides includes metallic substrates, a blue chip, golden lines, light emitting materials and a reflective white adhesive layer. The metallic substrates include a first metallic substrate and a second metallic substrate. A transparent holder is fixated with the first metallic substrate and the second metallic substrate, forming a containing cavity. A light emitting chip is across disposed on the first metallic substrate and the second metallic substrate. The light emitting materials are filled in the containing cavity and covering the blue chip. The reflective white adhesive layer is disposed on a top surface of the light emitting materials. The LED emitting light on four sides provided by the disclosure is simply manufactured and low in costs.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 11, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yong Fan
  • Patent number: 10312279
    Abstract: Multi-photodiode image pixels may include sub-pixels with differing light sensitivities. Microlenses may be formed over the multi-photodiode image pixels so that light sensitivity of sub-pixels in an outer group of sub-pixels is enhanced. To prevent high angle light incident upon one of the sub-pixels of the image pixel from generating charges in a photosensitive region of another sub-pixel of the image pixel, intra-pixel isolation structures may be formed. Intra-pixel isolation structures may surround, and in some embodiments, overlap the light collecting region of an inner photodiode. When the intra-pixel isolation structures have a different index of refraction than light filtering material formed adjacent to the isolation structures, high angle light incident upon the isolation structures may be reflected back into the sub-pixel it was initially incident upon.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 4, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Swarnal Borthakur, Marc Allen Sulfridge
  • Patent number: 10305011
    Abstract: A light emitting apparatus includes a package having a long-length direction and a short-length direction perpendicular to the long-length direction as viewed in plan view. The package includes first and second leadframes and a resin portion. The first leadframe has a first leadframe main portion and a first leadframe extension portion which has narrower width than that of the first leadframe main portion. The second leadframe has a second leadframe main portion and a second leadframe extension portion which has narrower width than that of the second leadframe main portion. An inclined portion is formed between the first leadframe and the second leadframe as viewed in plan view. An upper end of the inclined portion is shifted from a lower end of the inclined portion.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: May 28, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Shimpei Sasaoka, Takuya Nakabayashi
  • Patent number: 10297606
    Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: May 21, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
  • Patent number: 10294095
    Abstract: A micromechanical sensor that is produced surface-micromechanically includes at least one mass element formed in a third functional layer that is non-perforated at least in certain portions. The sensor has a gap underneath the mass element that is formed by removal of a second functional layer and at least one oxide layer. The removal of the at least one oxide layer takes place by introducing a gaseous etching medium into a defined number of etching channels arranged substantially parallel to one another. The etching channels are configured to be connected to a vertical access channel in the third functional layer.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: May 21, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Benny Pekka Herzogenrath, Johannes Classen
  • Patent number: 10276727
    Abstract: A semiconductor integrated circuit device includes first and second select gate electrodes that are sidewall-shaped along sidewalls of a memory gate structure. With this configuration, the memory gate structure is not disposed on the first select gate electrode and the second select gate electrode. Accordingly, the memory gate structure the first select gate structure, and the second select gate structure can have equal heights, thereby achieving reduction in size as compared to a conventional case. In addition, a silicide layer on the first select gate electrode and a silicide layer on the second select gate electrode can be separated farther from a memory gate electrode by the thickness of a cap film. Accordingly, the silicide layers on the first select gate electrode and the second select gate electrode are unlikely to contact with the memory gate electrode, thereby preventing a short-circuit defect of the memory gate electrode.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 30, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Fukuo Owada, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 10276507
    Abstract: An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of the substrate, a first conductive layer is disposed on the first surface of the substrate, and a second conductive layer is disposed on the second surface of the substrate and is electrically connected to the first conductive layer by the first conductive component. A die is disposed in a through hole in the substrate. A back surface of the die is exposed from the second surface of the substrate. A first dielectric layer covers an active surface of the die and the first surface of the substrate. A third conductive layer is disposed on the first dielectric layer and is electrically connected to the die by a second conductive component. A first metal layer is disposed directly on the back surface of the die.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 30, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Cheng Lee, Hsing Kuo Tien
  • Patent number: 10276682
    Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wei Yao, Chen-Ju Yu, King-Yuen Wong, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Chih Yang, Chun Lin Tsai
  • Patent number: 10276669
    Abstract: A semiconductor device includes a base layer, a dielectric layer over the base layer, an opening extending through the dielectric layer and to a main surface of the base layer, the opening having a sloped sidewall, and an electrically conductive material over the sloped sidewall. An angle between the sloped sidewall and the main surface of the base layer is in a range between 5 degrees and 50 degrees. Corresponding methods of manufacturing the semiconductor device are also provided.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: April 30, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Ulrich Heinle, Gerhard Prechtl, Gilberto Curatola
  • Patent number: 10276642
    Abstract: Disclosed are a top-emitting OLED display unit, a method for manufacturing the same, and a display panel. The top-emitting OLED display unit includes a first electrode serving as a common electrode, a light-emitting material layer disposed above the first electrode, and a second electrode disposed above the light-emitting material layer, the second electrode serving as a pixel electrode. A manufacture process of the first electrode and the second electrode can be simplified by means of the OLED display unit, and it is beneficial for reducing consumption of electrode materials.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 30, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Yuejun Tang
  • Patent number: 10276751
    Abstract: A light emitting element has semiconductor layers and first and second electrodes disposed. In plan view, the first electrode has a first connecting portion, a first extending portion, and two second extending portions, and the second electrode has a second connecting portion and two third extending portions. The first extending portion of the first electrode extends linearly from the first connecting portion toward the second connecting portion, and the two second extending portions extend parallel to the first extending portion on two sides of the first extending portion. The second extending portions each has two bent portions. The third extending portions extend parallel to the first extending portion between the first extending portion and the second extending portion. With respect to an extending direction of the first extending portion, each of the second extending portions extends beyond a position of the second connecting portion.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: April 30, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Kosuke Sato, Keiji Emura
  • Patent number: 10269659
    Abstract: A semiconductor structure and a fabrication method are provided. A fabrication method includes providing a substrate including an NMOS region and a PMOS region; forming a first high-K gate dielectric layer on the NMOS region of the substrate; forming an interfacial layer on the PMOS region of the substrate; forming a second high-K gate dielectric layer on the interfacial layer and the first high-K gate dielectric layer; forming a metal layer on the second high-K gate dielectric layer.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 23, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10269889
    Abstract: An electronic device including a base structure, a first pattern having at least one projection disposed on the base structure, a first conductive layer including a first portion disposed on the base structure and a second portion disposed on the first pattern and connected to the first portion, an insulating layer disposed on the first conductive layer covering the first portion and exposing the second portion, and a second conductive layer provided on the insulating layer and overlapping the first conductive layer. The second conductive layer is spaced apart from the first portion and is in contact with the second portion. Methods of manufacturing an electronic device capable of reducing the number of process steps in the manufacturing process are also disclosed.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: April 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sungkyun Park, Jungha Son, Sangkyu Choi
  • Patent number: 10269910
    Abstract: A method of manufacturing a semiconductor device, the method comprising: forming trenches in an upper surface of a semiconductor substrate, the semiconductor substrate comprising a first region and a second region, the trenches in the first region having a wide width, and the trenches in the second region having a narrow width; forming insulating films on inner surfaces of the trenches; filling conductive material inside the trenches; etching the conductive material until each of upper surfaces of the conductive material filled inside the trenches becomes lower than the upper surface of the semiconductor substrate; and forming, after the etching of the conductive material, an impurity layer by implanting impurities to a predetermined depth range, the impurity layer having a concentration by which a conductivity type of a region opposed to the conductive material via each insulating film is inverted by a potential applied to the conductive material.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: April 23, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Shinya Iwasaki
  • Patent number: 10249662
    Abstract: The present disclosure provides a multispectral imaging device, comprising the following layers and components arranged in sequence following a direction of incident light: a color filter layer, comprising a plurality of color filters transparent for specific wavebands; a first transparent electrode layer continuously formed in imaging area; a first conversion layer continuously formed in imaging area to convert visible light to electric signals; a first flat topography comprising plurality of pixel electrodes and with surface roughness less than 5 nm; a second conversion layer to convert NIR light to electric signals; and circuit components to process the electric signals. Benefit from the first continuous conversion layer formed on the flat topography, high light utilization, low spectral cross-talk, low dark current are achieved in the multispectral imaging device.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: April 2, 2019
    Inventor: Zhongshou Huang
  • Patent number: 10249696
    Abstract: A display device includes: a substrate; a plurality of pixels provided in a pixel region of the substrate; a scan line and a data line, connected to each of the plurality of pixels; a first transistor connected to the scan line and the data line and a second transistor connected to the first transistor; a light emitting element connected to the transistor; a first blocking layer disposed between the substrate and the first transistor, the first blocking layer being electrically connected to the first transistor; and a second blocking layer disposed between the substrate and the second transistor, the second blocking layer being electrically connected to the second transistor, wherein the first blocking layer is connected to a gate electrode of the first transistor, and the second blocking layer is connected to any one of source and drain electrodes of the second transistor.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: April 2, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Il Joo Kim, Cheol Gon Lee, Mee Hye Jung
  • Patent number: 10243006
    Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takeshi Osada, Shunpei Yamazaki
  • Patent number: 10243020
    Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 10236331
    Abstract: Although an organic resin substrate is highly effective at reducing the weight and improving the shock resistance of a display device, it is required to improve the moisture resistance of the organic resin substrate for the sake of maintaining the reliability of an EL element. Hard carbon films are formed to cover a surface of the organic resin substrate and outer surfaces of a sealing member. Typically, DLC (Diamond Like Carbon) films are used as the carbon films. The DLC films have a construction where carbon atoms are bonded into an SP3 bond in terms of a short-distance order, although the films have an amorphous construction from a macroscopic viewpoint. The DLC films contain 95 to 70 atomic % carbon and 5 to 30 atomic % hydrogen, so that the DLC films are very hard and minute and have a superior gas barrier property and insulation performance.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai