Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

Abstract: Polymeric films, which may be adhesive films, and display devices including such polymeric films, wherein a polymeric film includes: a first polymeric layer having two major surfaces, wherein the first polymeric layer includes a first polymeric matrix and particles. The first polymeric layer includes: a first polymeric matrix having a refractive index n1; and particles having a refractive index n2 uniformly dispersed within the first polymeric matrix; wherein the particles are present in an amount of less than 30 vol-%, based on the volume of the first polymeric layer, and have a particle size range of 400 nanometers (nm) to 3000 nm; and wherein n1 is different than n2.

Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.

Abstract: A display substrate includes a substrate, a first gate electrode on the substrate, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, a second gate electrode on the second gate insulating layer, an interlayer insulating layer on the second gate electrode, a first electrode on the interlayer insulating layer to contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer, and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

Abstract: A highly reliable display apparatus is provided. In an EL display apparatus including a specific pixel having a function of adding data, a storage node is provided in the pixel, and first data can be held in the storage node. In the pixel, second data is added to the first data through capacitive coupling, whereby third data can be generated. A light-emitting device operates in accordance with the third data. In the pixel, a light-emitting device that requires a high voltage for light emission or a light-emitting device to which application of a high voltage is preferred is provided.

Abstract: A display device includes: a first semiconductor layer on a first buffer layer, and including a first active layer; a first gate insulating layer on the first semiconductor layer, and covering the first active layer; a first conductive layer on the first gate insulating layer, and including a first gate electrode; a second conductive layer on the first conductive layer, and including a first source/drain electrode; a first interlayer insulating layer on the first conductive layer; a second semiconductor layer on the first interlayer insulating layer, and including a second active layer; a second gate insulating layer on the second semiconductor layer, and covering the second active layer; and a third conductive layer on the second gate insulating layer, and including a second gate electrode and a second source/drain electrode. The first gate insulating layer and the second gate insulating layer include different insulating materials from each other.

Abstract: A flexible display panel and a manufacturing method which is capable of removing a non-display area without damaging a display element layer, the flexible display panel includes a flexible substrate which includes a display area and a peripheral area outside of the display area, a display element layer disposed on the flexible substrate, and a neutral plane balancing layer disposed on the display element layer in the peripheral area, wherein the peripheral area of the flexible substrate in which the neutral plane balancing layer is disposed is folded towards a rear side of the display area along a first bending line, and the neutral plane balancing layer overlaps the first bending line.

Abstract: Embodiments described herein include systems and techniques for converting (i.e., transducing) a quantum-level (e.g., single photon) signal between the three wave forms (i.e., optical, acoustic, and microwave). A suspended crystalline structure is used at the nanometer scale to accomplish the desired behavior of the system as described in detail herein. Transducers that use a common acoustic intermediary transform optical signals to acoustic signals and vice versa as well as microwave signals to acoustic signals and vice versa. Other embodiments described herein include systems and techniques for storing a qubit in phonon memory having an extended coherence time. A suspended crystalline structure with specific geometric design is used at the nanometer scale to accomplish the desired behavior of the system.

Abstract: A hetero-junction phototransistor with a first layer comprising an InP N buffer and substrate, a second layer comprising an InGaAs N collector on the InP N buffer and substrate, a plurality of InGaAs P bases on the InGaAs N collector layer, and a plurality of InAIAs N emitters is described. Each emitter of the plurality of InAIAs N emitters is on a different base of the plurality of InGaAs P bases. The hetero-junction phototransistor comprises a plurality of InGaAs N+ caps, wherein each cap of the plurality of InGaAs N+ caps is on a different emitter of the plurality of InAIAs N emitters. The hetero-junction phototransistor comprises one or more electrical contacts. Each of the one or more electrical contacts is on a different cap of the plurality of InGaAs N+ caps.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a channel layer and a barrier layer that are sequentially superimposed, and a gate region being defined on a surface of the barrier layer; and a p-type semiconductor material layer formed in the gate region, the p-type semiconductor material layer including at least one composition change element, and a component of the composition change element changing along an epitaxial direction.

Abstract: The present application provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a channel layer, a barrier layer located on the channel layer, a composition change layer located on the barrier layer, and a p-type semiconductor material layer located in the gate region of the composition change layer, wherein a gate region is defined on a surface of the composition change layer, and a material of the composition change layer includes at least one composition change element.

Abstract: A display panel includes a pixel structure, including a plurality of pixel groups, and the pixel group includes: a first switch, having a second end coupled to a first main pixel; a second switch, having a second end coupled to a first sub-pixel; a third switch, having a second end coupled to the first sub-pixel; a first capacitor, having one end coupled to a first end of the third switch and another end coupled to a common electrode; and a fourth switch, having a second end coupled to a second main pixel; a fifth switch, having a second end coupled to a second sub-pixel; a sixth switch, having a second end coupled to the second sub-pixel; a second capacitor, having one end coupled to a first end of the sixth switch and another end coupled to the common electrode.

Abstract: A new and useful p-type oxide semiconductor with a wide band gap and an enhanced electrical conductivity and the method of manufacturing the p-type oxide semiconductor are provided. A method of manufacturing a p-type oxide semiconductor including: generating atomized droplets by atomizing a raw material solution containing at least a d-block metal in the periodic table and a metal of Group 13 of the periodic table; carrying the atomized droplets onto a surface of a base by using a carrier gas; causing a thermal reaction of the atomized droplets adjacent to the surface of the base under an atmosphere of oxygen to form the p-type oxide semiconductor on the base.

Abstract: A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.

Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a first III-V layer over the substrate, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes a second III-V layer over the first III-V layer, wherein the second III-V layer has a second dopant type opposite the first dopant type. The semiconductor structure further includes a third III-V layer over the second III-V layer, wherein the third III-V layer has the first dopant type. The semiconductor structure further includes a fourth III-V layer over the third III-V layer, the fourth III-V layer having the second dopant type. The semiconductor structure further includes an active layer over the fourth III-V layer. The semiconductor structure further includes a dielectric layer over the active layer.

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

Abstract: A first oxide semiconductor thin-fil transistor includes a top gate electrode, a first metal oxide film, and a top gate insulating film between the top gate electrode and the first metal oxide film. A second oxide semiconductor thin-film transistor includes a bottom gate electrode, a second metal oxide film, and a bottom gate insulating film between the bottom gate electrode and the second metal oxide film. A storage capacitor stores a signal voltage to the bottom gate electrode. A first electrode of the storage capacitor includes a part of the bottom gate electrode. A source/drain region of the first oxide semiconductor thin-film transistor is in contact with the bottom gate electrode in a contact hole in the bottom gate insulating layer. Capacitance per unit area of the bottom gate insulating film is smaller than capacitance per unit area of the top gate insulating film.

Abstract: A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, a first gate electrode, a second gate electrode, a first control transistor part, a gate interconnect, and a control gate interconnect. The semiconductor member includes first and second semiconductor layers. The semiconductor member includes first and second regions, and a first control region. The first and second gate electrodes extend along a first direction. A direction from the first region toward at least a portion of the first gate electrode is along a second direction crossing the first direction. The first control transistor part includes a first control gate electrode and a first control drain electrode. The first control drain electrode is electrically connected to the first and second gate electrodes. The gate interconnect is electrically connected to the first and second gate electrodes. The control gate interconnect is electrically connected to the first control gate electrode.

Abstract: At least one embodiment of the present disclosure relates to an array substrate and a manufacturing method thereof, a display panel and a display device. The array substrate includes: a pixel region including a first light emitting material layer; a hole region; a separating region including a separating structure, wherein the separating structure includes at least one first groove, and the separating structure is configured to separating the first light emitting material layer from the hole region through the first groove.