Abstract: A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.

Abstract: A thin film transistor substrate includes: a substrate, a first electrode disposed on the substrate, a bank disposed on the substrate and having an inclined surface inclined at an angle with respect to the substrate, a second electrode disposed on the bank, an active pattern electrically connected to the first electrode and the second electrode, disposed on the inclined surface, and including a first conductive region and a second conductive region in which impurities are doped, and a channel region between the first conductive region and the second conductive region, and a gate electrode overlapping at least a portion of the channel region of the active pattern. The inclined surface extends in a first direction in a plan view. The first conductive region, the channel region, and the second conductive region are sequentially disposed on the inclined surface along a second direction that crosses the first direction.

Abstract: A display device includes: a first electrode layer; a semiconductor layer including a source region, a drain region, and a channel region, wherein at least a portion of the source region or the drain region overlaps the first electrode layer; a second electrode layer arranged adjacent to the channel region; a third electrode layer overlapping the second electrode layer and at least a portion of the source region or the drain region; and a power line electrically connected to the first electrode layer and the third electrode layer.

Abstract: A display device including a substrate including a first display region having a first width, a second display region having a second width smaller than the first width, a peripheral region at a periphery of the first and second display regions, and a dummy region in the peripheral region, a first pixel in the first display region, a second pixel in the second display region, a first control line connected to the first pixel and extending in the first display region, a second control line connected to the second pixel and extending in the second display region, and a dummy line connected to the second control line in the dummy region, wherein the second control line is at a first conductive layer on a first insulating layer, the dummy line is at a second conductive layer on a second insulating layer on the first conductive layer.

Abstract: Different isolation liners for different type FinFETs and associated isolation feature fabrication are disclosed herein. An exemplary method includes performing a fin etching process on a substrate to form first trenches defining first fins in a first region and second trenches defining second fins in a second region. An oxide liner is formed over the first fins in the first region and the second fins in the second region. A nitride liner is formed over the oxide liner in the first region and the second region. After removing the nitride liner from the first region, an isolation material is formed over the oxide liner and the nitride liner to fill the first trenches and the second trenches. The isolation material, the oxide liner, and the nitride liner are recessed to form first isolation features (isolation material and oxide liner) and second isolation features (isolation material, nitride liner, and oxide liner).

Abstract: A high electron mobility transistor (HEMT) includes a GaN epi-layer, a first passivation layer, a source electrode metal, a drain electrode metal, a gate electrode metal, and a field plate. The first passivation layer is deposited on the GaN epi-layer. The source electrode metal, the drain electrode metal, and the gate electrode are recessed into the first passivation layer and deposited on the GaN epi-layer. The source electrode metal has a source field plate with a source field plate length Lsf. The drain electrode metal has a drain field plate with a drain field plate length Ldf, wherein Ldf>Lsf. The gate electrode is situated between the source electrode metal and the drain electrode metal. The field plate is situated between the gate electrode and the drain electrode metal.

Abstract: A display device includes a substrate, a first semiconductor pattern, a first gate insulating film covering the first semiconductor pattern, a first conductive layer and a second semiconductor pattern are on the first gate insulating film, a second gate insulating film on the second semiconductor pattern, a third gate insulating film covering the first gate insulating film and the second gate insulating film, a second conductive layer on the third gate insulating film, an interlayer insulating film covering the second conductive layer, and a third conductive layer on the interlayer insulating film, wherein the first and second semiconductor patterns respectively form semiconductor layers of the first and second transistors, wherein the first conductive layer includes a gate electrode of the first transistor and a first electrode of the capacitor, and wherein the second conductive layer includes a gate electrode of the second transistor and a second electrode of the capacitor.

Abstract: The present application provides an organic light-emitting diode (OLED) display panel and an electronic device. A projection of a touch electrode of the OLED display panel projected on a base substrate is at least partially overlapped with a projection of a support pillar projected on the base substrate. The support pillar includes at least one side surface. An angle between an upper top surface of the support pillar is less than or equal to 90 degrees, and/or an angle between the side surface and a lower bottom surface of the support pillar is greater than or equal to 90 degrees. A common electrode layer is disconnected at the support pillar. Accordingly, the present application improves a report rate for touch control and enhances touch sensitivity of the OLED display panel.

Abstract: The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The barrier layer comprises a doped semiconductor region extending from a top surface to a bottom surface of the barrier layer and located between the drain and the gate conductor.

Abstract: A display apparatus includes a substrate including a display area in which a display element is arranged, a first thin-film transistor arranged in the display area and including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, the first semiconductor layer including a silicon semiconductor, a first interlayer insulating layer covering the first gate electrode, a second thin-film transistor on the first interlayer insulating layer and including a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer including an oxide semiconductor, and an upper electrode arranged on the first interlayer insulating layer and including a same material as that of the second semiconductor layer and at least overlapping the first gate electrode.

Abstract: A display device comprises a substrate including emission areas, and light blocking areas adjacent to the emission areas, a thin film transistor layer comprising a thin film transistor disposed on the substrate, and a connection line electrically connected to the thin film transistor, a light emitting element layer disposed on the thin film transistor layer and comprising light emitting elements corresponding to the emission areas, an encapsulation layer overlapping the light emitting element layer, and a pad portion disposed on the encapsulation layer and in electrical contact with the connection line through a contact hole in the encapsulation layer.

Abstract: An organic light emitting diode display includes a substrate including a display area and a pad area, a first thin film transistor disposed on the display area, an organic light emitting diode connected to the first thin film transistor, a pad electrode disposed on the pad area and a pad contact electrode disposed on an upper portion of the pad electrode and electrically connected to the pad electrode. The organic light emitting diode includes an anode, an organic emission layer, and a cathode. The anode includes a lower layer, an intermediate layer, and an upper layer. The pad contact electrode is formed of a material of the lower layer of the anode.

Abstract: A light emitting element includes a semiconductor structure, and first and second electrodes. In a plan view, the first electrode has a first connecting portion, and a first extending portion and exactly two second extending portions. The second electrode has a second connecting portion, and exactly two third extending portions. The first extending portion extends linearly from the first electrode connecting portion toward the second electrode connecting portion. Each of the two third extending portions includes a bent portion, and a linear portion located between the first extending portion and a respective one of linear portions of the two second extending portions, and along an imaginary line that extends through the two second extending portions and the two third extending portions in a direction perpendicular to the direction in which the first extending portion extends, an entirety of the second electrode is located inward of the two second extending portions.

Abstract: A light emitting device includes a ceramic substrate, a light emitting element, and a wiring. The light emitting element is formed on an upper surface of the ceramic substrate. The wiring is arranged inside the ceramic substrate and is electrically and directly connected to the light emitting element. The light emitting element includes a structure in which a lower semiconductor layer, an active layer, and an upper semiconductor layer are sequentially stacked.

Abstract: Semiconductor structures and methods of forming semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a semiconductor substrate and a III-nitride material region over a top surface of the semiconductor substrate. The semiconductor substrate includes a bulk region below the top surface and a parasitic channel that extends to a depth from the top surface toward the bulk region of the semiconductor substrate. The parasitic channel comprises a first region and a second region. The first region of the parasitic channel comprises an implanted species having a relative atomic mass of less than 5, and the second region of the parasitic channel is free from the implanted species or the implanted species is present in the second region at a concentration that is less than in the first region.

Abstract: An emissive display device includes a polycrystalline semiconductor including a channel, source region, and drain region of a driving transistor disposed on a substrate. The device includes a gate electrode of the driving transistor overlapping the channel of the driving transistor, an oxide semiconductor including a channel, a source region, and a drain region of a second transistor disposed on the substrate, and a first connection electrode. The first connection electrode includes a first connector electrically connected to the gate electrode of the driving transistor, a second connector electrically connected to a second electrode of the second transistor, and a main body disposed between the first connector and the second connector. The device includes an initialization voltage line disposed on the substrate and applying an initialization voltage. The initialization voltage line surrounds at least a part of the second connector of the first connection electrode.

Abstract: Disclosed herein is a solid-state imaging device including: a laminated semiconductor chip configured to be obtained by bonding two or more semiconductor chip sections to each other and be obtained by bonding at least a first semiconductor chip section in which a pixel array and a multilayer wiring layer are formed and a second semiconductor chip section in which a logic circuit and a multilayer wiring layer are formed to each other in such a manner that the multilayer wiring layers are opposed to each other and are electrically connected to each other; and a light blocking layer configured to be formed by an electrically-conductive film of the same layer as a layer of a connected interconnect of one or both of the first and second semiconductor chip sections near bonding between the first and second semiconductor chip sections. The solid-state imaging device is a back-illuminated solid-state imaging device.

Abstract: Disclosed is a display device having improved reliability. The display device includes a first transistor disposed on a substrate, an electrical property of the first transistor being shifted from a first initial value in a decreasing direction; a second transistor disposed on the substrate, an electrical property of the second transistor being shifted from a second initial value in an increasing direction; and a first upper barrier conductive layer disposed so as to overlap a first active layer of the first transistor and not to overlap a second active layer of the second transistor, whereby reliability of each of the first and second transistors is improved.

Abstract: A display apparatus includes a first pad at one side of a substrate; a first semiconductor layer on the substrate; a first crack detection electrode interposed between the substrate and the first semiconductor layer, and including a first end portion at the one side and a second end portion at another side; a second crack detection electrode disposed on the first semiconductor layer, and including a first end portion located at the one side and a second end portion connected to the second end portion of the first crack detection electrode; and a first auxiliary electrode disposed on the second conductive layer, and including a first end portion connected to the second end portion of the first crack detection electrode and a second end portion electrically connected to the first pad.

Abstract: The HEMT includes a channel layer, a barrier layer, a drain, and a gate conductor. The barrier layer is disposed on the channel layer. The drain is disposed on the barrier layer. The gate conductor is disposed on the barrier layer. The channel layer includes a doped semiconductor structure overlapping with a top surface of the channel layer and having a bottom-most border that is located over a bottom-most surface of the channel layer and is spaced apart from the bottom-most surface of the channel layer. The doped semiconductor structure is located between the drain and the gate conductor.