Patents Examined by Tan N. Tran
  • Patent number: 10243006
    Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 26, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takeshi Osada, Shunpei Yamazaki
  • Patent number: 10243020
    Abstract: A magnetic random access memory (MRAM) device includes a conductor disposed in an insulating material of a lower wiring layer, a magnetic tunnel junction (MTJ) structure formed in an upper wiring layer, and a landing pad formed in an intermediary wiring layer between the lower and upper wiring layers, the landing pad extending from a top surface of the conductor to a height above the intermediary wiring layer, wherein the landing pad connects the MJT structure to the conductor.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 10236331
    Abstract: Although an organic resin substrate is highly effective at reducing the weight and improving the shock resistance of a display device, it is required to improve the moisture resistance of the organic resin substrate for the sake of maintaining the reliability of an EL element. Hard carbon films are formed to cover a surface of the organic resin substrate and outer surfaces of a sealing member. Typically, DLC (Diamond Like Carbon) films are used as the carbon films. The DLC films have a construction where carbon atoms are bonded into an SP3 bond in terms of a short-distance order, although the films have an amorphous construction from a macroscopic viewpoint. The DLC films contain 95 to 70 atomic % carbon and 5 to 30 atomic % hydrogen, so that the DLC films are very hard and minute and have a superior gas barrier property and insulation performance.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuyuki Arai
  • Patent number: 10236279
    Abstract: A method is provided for fabricating an emissive display substrate with a light management system. The method provides a transparent first substrate with a top surface and forms a plurality of emissive element wells. The well sidewalls are formed from a light absorbing material or a light reflector material. In one aspect, a light blocking material film layer is formed overlying the first substrate top surface, and the emissive element sidewalls are formed in the light blocking material film layer. In another aspect, a transparent second substrate is formed overlying the first substrate top surface. Then, the emissive element wells are formed in the second substrate with via surfaces, and the light blocking material is deposited overlying the well via surfaces. Additionally, the light blocking material may be formed on the bottom surface of each well. An emissive display substrate with light management system is provided below.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: March 19, 2019
    Assignee: eLux, Inc.
    Inventors: Kurt Ulmer, Paul J. Schuele, Kenji Sasaki, Jong-Jan Lee
  • Patent number: 10236388
    Abstract: A dual gate oxide thin-film transistor and manufacturing method for the same. The thin-film transistor comprises: a substrate; a bottom gate electrode formed on the substrate; a first gate insulation layer disposed on the bottom gate electrode; a semiconductor layer formed on the first gate insulation layer; a second gate insulation layer formed on the semiconductor layer; and a top gate electrode formed on the second gate insulation layer; wherein, the transistor further comprises a data line, the data line and the bottom gate electrode, or the data line and the top gate electrode are located at a same metal layer. Because the data line and the bottom gate (or the top gate) electrodes are located at a same metal layer, and through one photolithography for patterning to reduce the number of the mask, decrease the production cost. Besides, the stability and the response speed are increased.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: March 19, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Yingtao Xie
  • Patent number: 10222663
    Abstract: The present disclosure provides an array substrate and a method of manufacturing the same, and a display panel. In an embodiment, an array substrate includes: gate lines and data lines on a base substrate; and sub-pixels defined by the gate lines and the data lines and each including a pixel electrode and a common electrode. One of the pixel electrode and the common electrode, which is away from the base substrate, includes a plurality of electrically connected electrode strips, and there is a pitch between any adjacent two of the electrode strips in a horizontal direction. The array substrate further comprises a metal wire in the sub-pixel, and the metal wire is located in a region between the pixel electrode and the data line.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: March 5, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Xibin Shao, Hongtao Lin
  • Patent number: 10224435
    Abstract: An exemplary embodiment of the present disclosure provides a transistor including: a drain electrode; a first insulating member on the drain electrode and having a tilted side wall; a source electrode on the first insulating member; an active member covering the tilted side wall of the first insulating member, a side wall of the source electrode, and a side wall of the drain electrode; a second insulating member covering the source electrode and the active member; and a gate electrode on the second insulating member and overlapping the active member, wherein the active member defines a first channel region adjacent to the drain electrode and a second channel region adjacent to the source electrode, and wherein a width of the first channel region may be greater than that of the second channel region.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: March 5, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jee Hoon Kim, Shin Hyuk Yang, Kwang Soo Lee
  • Patent number: 10217777
    Abstract: A display device according to the present disclosure includes: a transistor section (100) that includes a gate insulating film (130), a semiconductor layer (140), and a gate electrode layer (120), the semiconductor layer being laminated on the gate insulating film, the gate electrode film being laminated on an opposite side to the semiconductor layer of the gate insulating film; a first capacitor section (200) that includes a first metal film (210) and a second metal film (220), the first metal film being disposed at a same level as wiring layers (161, 162) that are electrically connected to the semiconductor layer and is disposed over the transistor section, the second metal film being disposed over the first metal film with a first interlayer insulating film (152) in between; and a display element that is configured to be controlled by the transistor section.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: February 26, 2019
    Assignee: Sony Corporation
    Inventors: Hitoshi Tsuno, Koichi Nagasawa
  • Patent number: 10211294
    Abstract: III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 19, 2019
    Assignee: MACOM Technology Solutions Holdings, Inc.
    Inventors: John Claassen Roberts, James W. Cook, Jr.
  • Patent number: 10205027
    Abstract: The present disclosure relates to a coplanar double gate electrode oxide thin film transistor, includes a substrate, a bottom gate electrode, a first gate electrode insulating layer, a oxide semiconductor layer, a source electrode contact area and a drain electrode contact area, a second gate electrode insulating layer and a top gate electrode, wherein, the upper surface of the substrate is recessed toward the inside of the substrate to form a groove, the bottom gate electrode is formed in the groove, so that the upper surface of the bottom gate electrode and the upper surface of the substrate are in the same horizontal plane. The thin film transistor of the present disclosure has the characteristics of the double gate electrode and the coplanar structure, and is capable of improving the stability of the thin film transistor, optimizing the response speed thereof, and lowering the driving voltage.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: February 12, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Yingtao Xie
  • Patent number: 10199400
    Abstract: The present disclosure provides an array substrate, a display panel and a display device. The array substrate includes a first conductive pattern and a second conductive pattern forming a ground (GND) protection circuit. The first conductive pattern includes a plurality of first conductive segments spaced apart from each other, and adjacent first conductive segments are connected to each other by the second conductive pattern, an insulating layer is arranged between the first conductive segments and the second conductive pattern, and the first conductive segments are connected to the second conductive pattern through via holes penetrating through the insulating layer. In addition, the present disclosure provides a display panel including the above array substrate. Furthermore, the present disclosure provides a display device including the above array substrate.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: February 5, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Jingyi Xu, Bo Yang, Yanwei Ren, Yu Liu, Xin Zhao, Yanyan Zhao, Erpeng Zhao, Zhiqiang Wang, Wei Zhang
  • Patent number: 10181479
    Abstract: The present invention provides a manufacturing method of an array substrate and an array substrate. The manufacturing method of the array substrate according to the present invention combines the COA technology and the BOA technology, where a black matrix is first formed on a backing plate, followed by forming a top-gate TFT device on the black matrix, and finally forming a color filter layer on the TFT device, wherein the pixel electrode is directly arranged on the drain electrode and connected with the drain electrode. The manufacturing method helps enhance electrical performance of a TFT device and stability of performance, improves quality of a display panel, and, compared to an existing array substrate manufacturing method, reduces masks and operations involved. The manufacturing method is simple and helps reduce manufacturing costs.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: January 15, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zhiwei Tan
  • Patent number: 10170316
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based transistor. A nanosheet stack is formed over a substrate. The nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A tri-layer gate metal stack is formed on each nanosheet. The tri-layer gate metal stack includes an inner nitride layer formed on a surface of each nanosheet, a doped transition metal layer formed on each inner nitride layer, and an outer nitride layer formed on each doped transition metal layer.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Paul C. Jamison
  • Patent number: 10170627
    Abstract: A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 1, 2019
    Assignee: Acorn Technologies, Inc.
    Inventors: Paul A. Clifton, Andreas Goebel, Walter A. Harrison
  • Patent number: 10164057
    Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Yub Jeon, Tae Yong Kwon, Oh Seong Kwon, Soo Yeon Jeong, Yong Hee Park, Jong Ryeol Yoo
  • Patent number: 10158095
    Abstract: A light emitting diode includes a first electrode overlapping a second electrode, an emission layer between the first and second electrodes. a first hole injection layer and a second hole injection layer between the first electrode and the emission layer, and a first hole transporting layer between the first hole injection layer and the second hole injection layer. Each of the first and second hole injection layers includes an inorganic dipole material. At least one of the first hole injection layer or the second hole injection layer including an organic material.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: December 18, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dong Chan Kim, Won Jong Kim, Ji Young Moon, Dong Kyu Seo, Myung Chul Yeo, Ji Hye Lee, Yoon Hyeung Cho
  • Patent number: 10157975
    Abstract: A method includes determining an active region pattern density of a first region of an integrated circuit layout based on a total area of each active region in the first region and an area of the first region. The method includes determining an active region pattern density of a second region of the integrated circuit layout based on a total area of each active region in the second region and an area of the second region. The method includes determining an active region pattern density gradient between the first region to the second region. The method includes determining whether the first region or the second region includes a resistive device. The method includes modifying a portion of the resistive device to include an incremental resistor in response to the first region or the second region including the resistive device.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Yu Ma, Chia-Hui Chen, Yi-Ting Wang
  • Patent number: 10153430
    Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure with reduced shifting in stored memory cell resistance levels over time are described. The BMC structure may comprise a reversible resistance-switching memory element within a memory array comprising a first conductive metal oxide (e.g., titanium oxide) in series with an alternating stack of one or more layers of an amorphous low bandgap material (e.g., germanium) with one or more layers of a second conductive metal oxide (e.g., aluminum oxide). The BMC structure may include a barrier layer comprising a first conductive metal oxide, such as titanium oxide or strontium titanate, in series with a germanium stack that includes a layer of amorphous germanium or amorphous silicon germanium paired with a second conductive metal oxide. The second conductive metal oxide (e.g., aluminum oxide) may be different from the first conductive metal oxide (e.g., titanium oxide).
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 11, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Deepak Kamalanathan, Juan Saenz
  • Patent number: 10153639
    Abstract: One example discloses an apparatus for power management, including: a current sink/source sensor configured to monitor a power-supply to inter-power-domain sink/source-current and to generate a current mismatch signal if the power-supply to inter-power-domain sink/source-current exceeds a threshold range; and a current imbalance controller coupled to receive the current mismatch signal and configured to generate a set of power-domain control signals; wherein the set of power-domain control signals reduce an absolute value of the power-supply to inter-power-domain sink/source-current.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: December 11, 2018
    Assignee: NXP B.V.
    Inventor: Ajay Kapoor
  • Patent number: 10141399
    Abstract: According to an embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first insulating layer, and a first insulating region. The second semiconductor region is provided on the first semiconductor region. The first insulating layer is provided around at least a portion of the first semiconductor region and at least a portion of the second semiconductor region. The first insulating layer contacts the second semiconductor region. The first insulating region is provided around at least a portion of the first insulating layer.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: November 27, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideki Okumura, Masanobu Tsuchitani, Hiroto Misawa, Akira Ezaki, Tatsuya Shiraishi