Abstract: Embodiments described herein include systems and techniques for converting (i.e., transducing) a quantum-level (e.g., single photon) signal between the three wave forms (i.e., optical, acoustic, and microwave). A suspended crystalline structure is used at the nanometer scale to accomplish the desired behavior of the system as described in detail herein. Transducers that use a common acoustic intermediary transform optical signals to acoustic signals and vice versa as well as microwave signals to acoustic signals and vice versa. Other embodiments described herein include systems and techniques for storing a qubit in phonon memory having an extended coherence time. A suspended crystalline structure with specific geometric design is used at the nanometer scale to accomplish the desired behavior of the system.

Abstract: Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.

Abstract: A method includes forming a fin protruding over a substrate; forming a conformal oxide layer over an upper surface and along sidewalls of the fin; performing an anisotropic oxide deposition or an anisotropic plasma treatment to form a non-conformal oxide layer over the upper surface and along the sidewalls of the fin; and forming a gate electrode over the fin, the conformal oxide layer and the non-conformal oxide layer being between the fin and the gate electrode.

Abstract: The present invention provides an array substrate and a display panel, the array substrate comprises: a first metal layer comprising a plurality of gate routings and a plurality of common electrode routings, at least one of the plurality of common electrode routings is arranged discontinuously and comprises a plurality of common electrode spacers spaced apart from each other; a second metal layer comprising a plurality of common electrode connecting portions; and a first insulating layer provided with a plurality of first through holes, adjacent two of the plurality of common electrode spacers are electrically connected to a common electrode connecting portion through two of the plurality of first through holes.

Abstract: A display device includes a substrate including a pixel area and a transmission area, and a pixel circuit disposed in the pixel area. The pixel circuit includes a first thin-film transistor included in a first multi-layer film, and a second thin-film transistor included in a second multi-layer film on the first multi-layer film. The first thin-film transistor and the second thin-film transistor are electrically connected to each other. The display device also includes a display element disposed on the second multi-layer film and including a pixel electrode electrically connected to the second thin-film transistor via a contact hole defined in the second multi-layer film, an opposite electrode facing the pixel electrode, and an intermediate layer between the pixel electrode and the opposite electrode.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanosheets spaced apart from each other and in a p-type device region, and a plurality of second semiconductor nanosheets spaced apart from each other and in an n-type device region. The semiconductor device includes an isolation structure formed at a boundary between the p-type and n-type device regions, and a first hard mask layer formed over the first semiconductor nanosheets. The semiconductor device also includes a second hard mask layer formed over the second semiconductor nanosheets, and a p-type work function layer surrounding each of the first semiconductor nanosheets and the first hard mask layer.

Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

Abstract: A display device includes: a substrate; a first conductive layer on the substrate and comprising a first signal line; an insulating layer pattern on the first conductive layer; a semiconductor pattern on the insulating layer pattern; a gate insulating layer on the semiconductor pattern; and a second conductive layer comprising a gate electrode on the gate insulting layer and a first source/drain electrode and a second source/drain electrode, each on at least a part of the semiconductor pattern, wherein the insulating layer pattern and the semiconductor pattern have a same planar shape, the semiconductor pattern comprises a channel region overlapping the gate electrode, a first source/drain region on a first side of the channel region and a second source/drain region on a second side of the channel region, and the first source/drain electrode electrically connects the first source/drain region and the first signal line.

Abstract: A chip is provided. The chip includes a flexible substrate, a plurality of thin-film transistors, a redistribution layer, a first power rail layer, and a second power rail layer. The plurality of thin-film transistors are disposed on the flexible substrate. The redistribution layer is disposed above the plurality of thin-film transistors. The first power rail layer is disposed above the redistribution layer. The first power rail layer provides a first voltage to the plurality of thin-film transistors. The second power rail layer is disposed above the first power rail layer. The second power rail layer provides a second voltage to the plurality of thin-film transistors, wherein the second power rail layer is disposed in a grid shape.

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

Abstract: Disclosed is a semiconductor device including a gate wiring, an active layer, a gate insulating film, a first wiring, a second wring, and a first semiconductor film. The gate wiring includes a gate electrode. The active layer overlaps with the gate electrode and contains an oxide semiconductor. The gate insulating film is sandwiched by the gate electrode and the active layer. The first wiring and the second wiring are each located over the active layer and respectively include a first terminal and a second terminal which are electrically connected to the active layer. The first semiconductor film is located under and in contact with the first wiring and contains the oxide semiconductor.

Abstract: The display apparatus includes a substrate, a first active layer disposed on the substrate, a first gate layer disposed on a layer covering the first active layer, the first gate layer including a first gate electrode, a second gate layer disposed on a layer covering the first gate layer, the second gate layer including an initialization line including a first part of a second electrode; a second active layer disposed on a layer covering the second gate layer, the second active layer including a second active region overlapping the first part of the second electrode; a third gate layer disposed on a layer covering the second active layer, the third gate layer including a second part of the second electrode overlapping the second active region; and a first source/drain layer disposed on a layer covering the third gate layer, the first source/drain layer including a first connection line.

Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a buffer layer over the substrate, wherein the buffer layer comprises a plurality of III-V layers, and a dopant type of each III-V layer of the plurality of III-V layers is opposite to a dopant of adjacent III-V layers of the plurality of III-V layers. The semiconductor structure further includes an active layer over the buffer layer. The semiconductor structure further includes a dielectric layer over the active layer.

Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a display area, including a first display area. The first display area includes light non-transmissive areas and light transmissive areas, and sub-pixels in the light non-transmissive areas include a first light-shielding layer, a pixel driving circuit, and a light-emitting structure layer. In a direction perpendicular to a substrate, a projection of the first light-shielding layer covers a projection of the light-emitting structure layer and a projection of at least one transistor of the pixel driving circuit.

Abstract: A display apparatus includes a first silicon transistor including a first semiconductor layer including a silicon-based semiconductor and a first gate electrode; a first oxide transistor including a second semiconductor layer and a second gate electrode, the second semiconductor layer including an oxide-based semiconductor; an upper insulating layer on the first and second semiconductor layers; and a first connection electrode on the upper insulating layer, electrically connected to the first semiconductor layer through a first contact hole of the upper insulating layer, and electrically connected to the second semiconductor layer through a second contact hole of the upper insulating layer. The second semiconductor layer includes a channel region, a source region, and a drain region, and a first distance between the channel region of the second semiconductor layer and the first contact hole is about 2 ?m or greater.

Abstract: Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.

Abstract: Flip chip LEDs comprise a transparent carrier and an active material layer such as AlInGaP bonded to the carrier and that emits light between about 550 to 650 nm. The flip chip LED has a first electrical terminal in contact with a first region of the active material layer, and a second electrical terminal in contact with a second region of the active material layer, wherein the first and second electrical terminals are positioned along a common surface of the active material layer. Chip-on-board LED packages comprise a plurality of the flip chip LEDs with respective first and second electrical terminals interconnected with one another. The package may include Flip chip LEDs that emit light between 420 to 500 nm, and the flip chip LEDs are covered with a phosphorus material comprising a yellow constituent, and may comprise a transparent material disposed over the phosphorus material.

Abstract: A display apparatus includes a thin film transistor facing a substrate with a buffer layer therebetween and including a semiconductor layer, a channel region, a source region, a drain region, and a gate electrode; a conductive pattern between the substrate and the semiconductor layer and connected to the semiconductor layer, the conductive pattern facing the semiconductor layer with the buffer layer therebetween; a contact hole in the buffer layer and exposing the conductive pattern to outside the buffer layer; and a display element which is electrically connected to the thin film transistor. The source region or the drain region extends through the contact hole in the buffer layer, to contact the conductive pattern and connect the semiconductor layer to the conductive pattern.