Abstract: A semiconductor apparatus comprises a gate electrode, a gate insulating layer, a drift region of a first conductivity type formed over a semiconductor substrate of the first conductivity type, a base region of a second conductivity type formed over the drift region, a source region of the first conductivity type formed on the base region and a column region formed in the drift region under the base region, the column region being divided into a plurality of divided portions in depth direction.

Abstract: A method of fabricating a semiconductor device is disclosed. First, a substrate is provided. The substrate includes at least a transistor area having a gate structure thereon, a capacitor area having a first electrode thereon and a resistor area having a second electrode thereon. The capacitor area and the resistor area both have an isolation structure therein. Then, first spacers and source/drain regions on both sides of the gate are sequentially formed. After that, a dielectric layer and a first conductive material layer are sequentially formed on the substrate. Next, the first conductive material layer is patterned to form a third electrode in the capacitor area and a conductive layer in the resistor area. Then, second spacers are formed. Afterwards, the exposed dielectric layer is removed. Finally, a self-aligned silicide process is performed to form a metal salicide layer to cover the surface of the device.

Abstract: Semiconductor materials including a gallium nitride material region and methods associated with such structures are provided. The semiconductor structures include a strain-absorbing layer formed within the structure. The strain-absorbing layer may be formed between the substrate (e.g., a silicon substrate) and an overlying layer. It may be preferable for the strain-absorbing layer to be very thin, have an amorphous structure and be formed of a silicon nitride-based material. The strain-absorbing layer may reduce the number of misfit dislocations formed in the overlying layer (e.g., a nitride-based material layer) which limits formation of other types of defects in other overlying layers (e.g., gallium nitride material region), amongst other advantages. Thus, the presence of the strain-absorbing layer may improve the quality of the gallium nitride material region which can lead to improved device performance.

Abstract: An LDMOS transistor includes a gate insulation film formed on a semiconductor substrate, a gate electrode formed on the gate insulation film, a drain well of a first conductivity type formed in the substrate so as to include a gate region covered with the gate electrode, a channel well of a second conductivity type formed in the drain well in a partially overlapped relationship with the gate region, a source region of the first conductivity type formed in the channel well in an overlapping manner or adjacent with a side surface of the gate electrode, a medium-concentration drain region of the first conductivity type having an intermediate concentration level and formed in the drain well at a side opposing to the source region in a manner partially overlapping with the gate region, the medium-concentration drain region being formed with a separation from the channel well, a drain region of the first conductivity type formed in the medium-concentration drain region with a separation from the gate region, a low

Abstract: High resistance elements of 5 K? or more are connected near first and second control terminals between the first and second control terminals and respective crossing portion of first and second connectings. Even when a high frequency analog signal transmitted in a pad wire leaks to the first and second connectings, the high frequency analog signal is attenuated by the high resistance elements. Accordingly, the high frequency analog signal is not substantially transmitted to control terminal pads. It is therefore possible to suppress an increase in insertion loss.

Abstract: A doped silicon block or island, formed above a drain electrode in substrate of a die or chip, has a height corresponding to the desired length of a channel. A source electrode is formed above the silicon island and allows for contact from above. Contact from above may also be made with an L-shaped control gate and with the subsurface drain. A horizontal array of contacts for source, gate and drain is formed for the vertical transistor that is built. If a layer of nanocrystals is incorporated into a layer between the gate and the channel, a non-volatile floating gate transistor may be formed. Without the layer of nanocrystals, an MOS or CMOS transistor is formed.

Abstract: In a memory cell (110) having multiple floating gates (160), the select gate (140) is formed before the floating gates. In some embodiments, the memory cell also has control gates (170) formed after the select gate. Substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions protrude above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed. A dielectric (164) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These the control gates and the floating gates are defined independently of photolithographic alignment. In another aspect, a nonvolatile memory cell has at least two conductive floating gates (160).

Abstract: An LED package includes a datum reference feature that is external to the insulating body of the LED package and has a known, fixed relationship to the heat sink. The LED die is mounted to the heat sink such that the LED die has a fixed relationship to the heat sink. Accordingly, the reference datum feature provides a frame of reference to the position of the LED die within the LED package. The reference datum feature may be mounted to the heat sink or integrally formed from the heat sink. A pick-and-place head holds the LED package by engaging the datum reference feature, e.g., with an alignment pin. In addition, the LED package may include a lead that extends laterally into the insulating body, and extends towards the LED die to reduce the vertical distance between the lead and the LED die.

Abstract: The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).

Abstract: An electronic sensor is provided for detecting the presence of one or more targets of interest in a sample. The sensor preferably comprises a special type of field effect transistor in which conductance is enhanced by target binding to recognition elements in the active region. An array of sensors may be formed to analyze a sample for multiple targets. The sensor may be used, for example, to detect the presence of pathogens, polypeptides, nucleic acids, toxins and other biochemical and chemical agents. The sensor is useful in a wide variety of applications including medical diagnostics, agriculture, public health, environmental monitoring and biomedical research.

Abstract: A solid-state imaging device can increase the amount of signal charge accumulation in a photodiode. The solid-state imaging device includes a gate electrode formed on a p-type semiconductor substrate. An n-type signal accumulation region accumulates the signal charge obtained through a photo-electrical conversion, and is formed in the semiconductor substrate so that a portion of the signal accumulation region is positioned below the gate electrode. An n-type drain region is positioned in the semiconductor substrate so that the n-type drain region is positioned opposite the signal accumulation region across the gate electrode. A p-type punch-through stopper region has a higher impurity concentration than the semiconductor substrate, and is formed in the semiconductor substrate so that the p-type punch-through region is positioned below the drain region, wherein an end of the punch-through stopper region is positioned closer to the signal accumulation region than the end of the drain region.

Abstract: A semiconductor memory element, which can be controlled via field effect, includes a semiconductor substrate of a first conduction type, a first doping region of a second conduction type provided in the semiconductor substrate, a second doping region of the second conduction type provided in the semiconductor substrate, a channel region located between the first and second doping regions, a multilayer gate dielectric which is arranged adjacent to the channel region and has a charge trapping memory layer, and a gate terminal provided above the gate dielectric. The charge trapping memory layer includes at least one sequence of adjacent layers, wherein the sequence of adjacent layers comprises an amorphous silicon carbide layer and an amorphous silicon nitride layer.

Abstract: A multi-bit memory cell (200) with a control gate (220) for controlling a middle portion of a channel region (208) provides improved operation including faster programming at smaller voltages and currents. The memory cell (200) includes a source (204) and a drain (206) diffused into a substrate (202) forming a channel region (208) therebetween. A first charge storing layer (214), a second charge storing layer (216) and the control gate (220) are formed on the substrate (202) over the channel region (208) and a gate (218) is formed over the source (204), the drain (206), the first and second charge storing layers (214, 216) and the control gate (220). Dielectric material (210, 212, 224, 226, 228) separates the source (204) and the drain (206) from the gate (218), and the control gate (220) from the first charge storing layer (214), the second charge storing layer (216) and the gate (218).

Abstract: A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

Abstract: An objective is to increase the reliability of a light emitting device structured by combining TFTs and organic light emitting elements. A TFT (1201) and an organic light emitting element (1202) are formed on the same substrate (1203) as structuring elements of a light emitting device (1200). A first insulating film (1205) which functions as a blocking layer is formed on the substrate (1203) side of the TFT (1201), and a second insulating film (1206) is formed on the opposite upper layer side as a protective film. In addition, a third insulating film (1207) which functions as a barrier film is formed on the lower layer side of the organic light emitting element (1202). The third insulating film (1207) is formed by an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, an aluminum oxide film, or an aluminum oxynitride film.

Abstract: A semiconductor storage element has a memory function body on opposite sides of a gate electrode formed on a semiconductor substrate. Each end of source/drain regions is located in the semiconductor substrate just under the memory function body and offset with respect to an edge of the gate electrode in a gate length direction to improve efficiency of electric charge injection into the memory function body. A storage state in the memory function body is found by detecting a amount of current between the source/drain regions, which current changes depending on the amount of the electric charge retained in the charge retention portion.

Abstract: A photovoltaic device includes at least a first electrode, a first-conductivity-type layer composed of non-single-crystalline silicon, a second-conductivity-type layer composed of polycrystalline silicon, a third-conductivity-type layer composed of non-single-crystalline silicon, and a second electrode, wherein the contact surface of the first electrode with respect to the first-conductivity-type layer has a shape interspersed with a plurality of projections, and the lower limit and the upper limit of the density of the projections interspersed on the surface of the first electrode satisfy the following equations, provided that the thickness of the second-conductivity-type layer is t ?m: Lower limit=0.312 exp(?0.60t) pieces/?m2 Upper limit=0.387 exp(?0.39t) pieces/?m2.

Abstract: The present invention aims at providing a heterojunction bipolar transistor having improved breakdown voltage on operation for high power output, and includes: a GaAs semiconductor substrate 100; an n+-type GaAs sub-collector layer 110; an n-type GaAs collector layer 120; a p-type GaAs base layer 130; an emitter layer 140; an n-type GaAs emitter cap layer 150; and an n-type InGaAs emitter contact layer 160. The emitter layer 140 has a multilayer structure including an n-type or non-doped first emitter layer 141 and an n-type second emitter layer 142 which are laminated in sequence. The first emitter layer 141 is made of a semiconductor material including Al, while the second emitter layer 142 is made of InxGa1-xP (0<x<1).

Abstract: A twin-cell type semiconductor memory device in which the area of a chip can be reduced. In the twin-cell type semiconductor memory device for storing data in at least one pair of memory cells as complementary information, memory cells are arranged at each of a plurality of word lines at intervals at which bit lines are located. At least the one pair of memory cells, which have stored the complementary information and which indicate a plurality of areas each connected to a pair of bit lines, form a twin cell.

Abstract: A capacitive dynamic quantity sensor whose size is small and whose reliability and mass productivity are high is provided. In order to realize signal transmission from a lower electrode to an upper electrode, silicon columns which are electrically isolated from one another but not mechanically isolated from one another are formed to connect both electrodes.