Patents Examined by Tariq Hafiz
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Patent number: 8230126Abstract: An apparatus comprises a digital image sensor, a communication port, a detection circuit and a processor. The detection circuit is configured to detect a change in electrical resistance at a connector of the communication port. The processor is configured to initiate an operation of the apparatus according to the detected change in resistance.Type: GrantFiled: October 27, 2009Date of Patent: July 24, 2012Assignee: Fairchild Semiconductor CorporationInventor: James A. Siulinski
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Patent number: 8205014Abstract: A tuning plan for a configuration of a resource of a storage system 5 is generated by acquiring configuration information of the resource of the storage system 5, and acquiring performance data of a reference value exceeding resource that is the resource having a utilization rate exceeding a preset reference value, and performance data of an analysis target resource that is a resource having a certain relationship with a reference value exceeding resource, and obtaining correlation degree between the reference value exceeding resource and the analysis target resources based on the performance data of the reference value exceeding resource and the performance data of the analysis target resources, and selecting a correlated analysis target resource that is the analysis target resource determined to have correlation with the reference value exceeding resource from the obtained correlation degree, and by calculating an average resource utilization rate of a resource group in a predetermined range on the basis ofType: GrantFiled: February 2, 2009Date of Patent: June 19, 2012Assignee: Hitachi, Ltd.Inventor: Kiyoshi Onuki
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Patent number: 8185670Abstract: An AV device control method and an AV device using the same. After receiving personal information gathered by an external device, an AV device is automatically controlled according to a user's personal information. Accordingly, the AV device can be customized to operate for an individual user.Type: GrantFiled: January 14, 2008Date of Patent: May 22, 2012Assignee: SAMSUNG Electronics Co., Ltd.Inventor: Kyung-soon Song
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Patent number: 8185668Abstract: A method of controlling an apparatus including a processor and an I/O controller includes storing execution information, receiving a first and a second requests successively, determining whether initiation of each execution of the first and the second requests is to be supervised by either of the processor and the I/O controller in reference to the execution information, transmitting the first request to the processor from the I/O controller, and upon completion of execution of the first request at the processor, transmitting the second request to the processor from the I/O controller when the initiations of executions of the first and second request is supervised by the I/O controller, and transmitting the first and second requests to the processor regardless of completion of execution of the first request by the processor when the initiations of executions of the first and second requests is supervised by the processor.Type: GrantFiled: October 29, 2009Date of Patent: May 22, 2012Assignee: Fujitsu LimitedInventors: Souta Kusachi, Go Sugizaki, Satoshi Nakagawa
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Patent number: 8185676Abstract: Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The I/O device driver determines whether the pending queue is sorted and responds to a determination that the pending queue is sorted, determining if queued I/O requests exceed the maximum ordered queue length. Responding to a determination that the pending queue exceeds the maximum ordered queue length, the I/O device driver adds the I/O request based on a high pointer, and points the high pointer to the I/O request.Type: GrantFiled: July 20, 2011Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: James P. Allen, Nicholas S. Ham, John L. Neemidge, Stephen M. Tee
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Patent number: 8180935Abstract: Methods and systems for encoding and/or decoding digital signals representing serial attached SCSI (SAS) out of band (OOB) signals exchanged over an optical communication between two SAS devices. A SAS OOB signal to be transmitted from a first SAS device to a second SAS device is first encoded as a digitally encoded signal representing the analog SAS OOB signal and then transmitted over an optical communication medium to another SAS device. A receiving SAS device coupled to an optical communication medium decodes a received digitally encoded signal to detect a received, encoded SAS OOB signal and processes the received SAS OOB signal when receipt is detected. The digitally encoded signal may comprise an idle word portion and a burst word portion to represent various SAS OOB signals. Further, the digitally encoded signal may be precomputed in a variety of disparity forms and stored in a memory for lookup and retrieval.Type: GrantFiled: May 22, 2009Date of Patent: May 15, 2012Assignee: LSI CorporationInventors: William K. Petty, Brian A. Day, Timothy E. Hoglund
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Patent number: 8171180Abstract: An information processing apparatus is disclosed that is connected to a device and generates data processable by the device based on device information about the device. The information processing apparatus includes a processing content setting unit that specifies, based on the device information, processing content to be executed by the device; a command retrieving unit that, if the processing content specified by the processing content setting unit contains unknown information, retrieves a command corresponding to the unknown information from the device information; and a data generating unit that generates, based on the command retrieved by the command retrieving unit and the processing content, data processable by the device.Type: GrantFiled: May 2, 2011Date of Patent: May 1, 2012Assignee: Ricoh Company, Ltd.Inventor: Akeo Maruyama
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Patent number: 8171178Abstract: A command is issued to a first data storage system for addressing a set of data and at least one of a first referral response including a referral to at least a second data storage system or at least a first subset of the set of data and the first referral response including the referral to the at least the second data storage system. The at least one of a first referral response is accessed. A command is issued to the second data storage system for addressing the set of data and a second referral response including a referral to at least one of the first data storage system and a third data storage system, the second data storage system including at least a second subset of the set of data. The second subset of the set of data and the second referral response including the referral to the at least one of the first data storage system or the third data storage system is accessed.Type: GrantFiled: September 3, 2009Date of Patent: May 1, 2012Assignee: LSI CorporationInventors: Ross E. Zwisler, Andrew J. Spry, Gerald J. Fredin, Kenneth J. Gibson
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Patent number: 8166207Abstract: In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining information of the processor complex responsive to the first write request, and transmitting a second write request from the processor complex to the peripheral device including the information. Other embodiments are described and claimed.Type: GrantFiled: September 29, 2008Date of Patent: April 24, 2012Assignee: Intel CorporationInventor: Bryan R. White
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Patent number: 8166217Abstract: A controller for interfacing a host and storage device is provided. The controller includes a channel that can receive data from the storage device in a first format and store the data in an intermediate buffer memory in a second format. The channel includes conversion logic that converts data from the first format to the second format and from the second format to the first format depending upon whether data is being read or written from the buffer memory. The conversion logic uses a shuttle register and shuttle counter for aligning data that is being transferred between the storage device and the buffer memory by appropriately concatenating data to meet the first and second format requirements. The first format is based on 10-bit symbols and the second format is based on 8-bits.Type: GrantFiled: June 28, 2004Date of Patent: April 24, 2012Assignee: Marvell International Ltd.Inventors: Theodore C. White, William W. Dennin, Angel G. Perozo
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Patent number: 8166215Abstract: Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed delay may be determined and introduced between the lanes. For this purpose the effective time “T” of the lanes is determined. The number of lanes “N” in the I/O interface is identified. The programmed lane to lane delay “D” is determined and a delay circuit having the programmed delay may be introduced between the lanes to reduce AC peak to peak noise in the I/O system.Type: GrantFiled: December 28, 2005Date of Patent: April 24, 2012Assignee: Intel CorporationInventors: Srikrishnan Venkataraman, Jayashree Kar, Sudarshan D. Solanki, Priyavadan Ramdas Patel, Michael M. DeSmith, David G. Figueroa
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Patent number: 8156263Abstract: An information processing apparatus includes: a processor configured to run an operating system; a plurality of storage devices connected to the processor; a detection module configured to detect a boot process for installing the operating system; a determination module configured to acquire device information from each of the storage devices and determine priority rank of the storage devices based on the device information when the detection module detects the boot process being originated from a device other than the storage devices; and a control module configured to install the operating system in a target storage device that is selected from among the storage devices, the target storage device having the highest priority rank determined by the determination module.Type: GrantFiled: January 7, 2010Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Keiichi Uehara
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Patent number: 8156252Abstract: In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.Type: GrantFiled: February 9, 2010Date of Patent: April 10, 2012Assignee: SMART Modular Technologies, Inc.Inventor: Ryan McDaniel
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Patent number: 8156258Abstract: A recording and replaying device is provided in which a user can easily diagnose failure when a built-in storage device of the device fails. In a normal operation state, a microcomputer controls a signal path switching mechanism to connect a signal processing device and a hard disk drive (HDD). In an abnormal operation state, the microcomputer sets a USB interface device to effective state, and controls the signal path switching mechanism to connect the USB interface device and the hard disk drive (HDD), so that the hard disk drive is recognized by an external personal computer as a USB mass storage.Type: GrantFiled: August 17, 2009Date of Patent: April 10, 2012Assignee: TEAC CorporationInventor: Norikazu Kunikata
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Patent number: 8151012Abstract: Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer.Type: GrantFiled: September 25, 2009Date of Patent: April 3, 2012Assignee: Intel CorporationInventors: Changkyu Kim, Albert Lin, Christopher J. Hughes, Anthony-Trung D. Nguyen, Yen-Kuang Chen, Zeshan A. Chishti, Bryan K. Casper
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Patent number: 8151015Abstract: Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a second storage section in an information transfer system. The information processing system includes the first storage section for storing the information, and a control section. The information transfer system includes: the second storage section for storing descriptor information indicating the location at which the information is stored in the first storage section and the size of the information; and a DMA transfer section for DMA transferring the information between the first storage section and the second storage section based on the descriptor information. The DMA transfer section DMA transfers the descriptor information concerning the DMA transferred information from the second storage section to the first storage section. The control section loads the descriptor information from the first storage section.Type: GrantFiled: July 10, 2008Date of Patent: April 3, 2012Assignee: Sony CorporationInventors: Tsuyoshi Kano, Mitsuki Hinosugi, Masato Kajimoto, Yoichi Mizutani
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Patent number: 8151013Abstract: A host I/F unit has a management table for managing an MPPK which is in-charge of the control of input/output processing for a storage area of an LDEV, and if a host computer transmits an input/output request for the LDEV, the host I/F unit transfers the input/output request to the MPPK which is in-charge of the input/output processing for the LDEV based on the management table, an MP of the MPPK performs the input/output processing based on the input/output request, and the MP of the MPPK also judges whether the MPPK that is in-charge of the input/output processing for the LDEV is to be changed, and sets the management table so that an MPPK which is different from the MPPK that is in-charge is to be in-charge of the input/output processing for the LDEV.Type: GrantFiled: February 15, 2011Date of Patent: April 3, 2012Assignee: Hitachi, Ltd.Inventors: Kazuyoshi Serizawa, Yasutomo Yamamoto, Norio Shimozono, Akira Deguchi, Hisaharu Takeuchi, Takao Sato, Hisao Homma
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Patent number: 8140715Abstract: A virtual media device is described for processing one or more input signals from one or more physical media input devices, to thereby generate an output signal for use by a consuming application module. The consuming application module interacts with the virtual media device as if it were a physical media input device. The virtual media device thereby frees the application module and its user from the burden of having to take specific account of the physical media input devices that are connected to a computing environment. The virtual media device can be coupled to one or more microphone devices, one or more video input devices, or a combination of audio and video input devices, etc. The virtual media device can apply any number of processing modules to generate the output signal, each performing a different respective operation.Type: GrantFiled: May 28, 2009Date of Patent: March 20, 2012Assignee: Microsoft CorporationInventors: Zicheng Liu, Rajesh K. Hegde, Philip A. Chou
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Patent number: 8140724Abstract: A hybrid controller and a method for coupling a plurality of host and memory devices with a hybrid controller are provided. In one embodiment, a hybrid controller may couple one or more host devices to one or more memory devices via multiple interface controllers, each interface controller configurable as a host or as a device. In one embodiment, interface controllers may have access to data across coupled devices as arbitrated by a buffer manager.Type: GrantFiled: August 18, 2009Date of Patent: March 20, 2012Assignee: Marvell International Ltd.Inventors: Tony Yoon, Chi Kong Lee
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Patent number: 8135895Abstract: A virtual SATA port multiplier and a virtual SATA device are provided for a SATA system. The virtual SATA port multiplier uses a SATA physical layer for data transfer between it and a SATA host, and a non-physical layer for direct data transfer between it and the virtual SATA device. Since the data transfer between the virtual SATA port multiplier and the virtual SATA device is not carried out by way of SATA physical layers, no physical layer circuits are required accordingly, thereby reducing the manufacturing cost, power consumption and hardware size of the SATA system.Type: GrantFiled: March 4, 2008Date of Patent: March 13, 2012Assignee: Skymedi CorporationInventors: Yung-Li Ji, Chin-Nan Yen, Fu-Ja Shone