Abstract: An integrated system to control peripherals in a vehicle includes a control and interconnection system having a supervisory processor and/or supervisory control. The control and interconnection system is responsive to feedback from peripherals associated with the vehicle. Moreover, the supervisory processor supervises a plurality of peripherals in communication with the control and interconnection system, where at least one of the plurality of the peripherals includes a controller and is associated with at least one of the: vehicle dynamics, vehicle power train and vehicle body, of a corresponding vehicle. Still further, the supervisory processor provides control information to each of the plurality of peripherals to coordinate performance characteristics based upon at least one operating condition that is determined by the control and interconnection system.

Abstract: A content-aware digital media storage device includes a host device interface for exchanging digital information with a host device, a memory array for storing digital information received from the host device via the host interface, a peripheral module configured to communicate the digital information stored in the memory array to a receiver located remote from the digital media storage device, and a controller communicatively coupled to the host device interface, the memory array and the peripheral module and configured to interpret directory information associated with the digital information stored in the memory array so as to selectively access said digital information and communicate such accessed digital information to the peripheral module for transmission to the remote receiver. Digital images stored in the memory array may be transmitted to a remote host via a wireless network access point with which the peripheral module of the storage device is associated.

Abstract: A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

Abstract: A technique for user notification involves modifying a title associated with a process to include information about an event that calls for user notification. A method according to the technique may include running a process, processing an event, generating a string of characters that includes information associated with the event, and displaying the string of characters as a title associated with the process. A system constructed according to the technique may include a client, a title array, an event processing engine, and a title provisioning engine.

Abstract: DMA in a computing environment that includes several computers and DMA engines, the computers adapted to one another for data communications by an data communications fabric, each computer executing an application, where DMA includes: pinning, by a first application, a memory region, including providing, to all applications, information describing the memory region; effecting, by a second application in dependence upon the information describing the memory region, DMA transfers related to the memory region, including issuing DMA requests to a particular DMA engine for processing; and unpinning, by the first application, the memory region, including insuring, prior to unpinning, that no additional DMA requests related to the memory region are issued, that all outstanding DMA requests related to the memory region are provided to a DMA engine, and that processing of all outstanding DMA requests related to the memory region and provided to a DMA engine has been completed.

Abstract: Disclosed is a computer implemented method and apparatus for queuing I/O requests to a pending queue. The I/O device driver sets a maximum ordered queue length for an I/O device driver coupled to a storage device then receives an I/O request from an application. The I/O device driver determines whether the pending queue is sorted and responds to a determination that the pending queue is sorted, determining if queued I/O requests exceed the maximum ordered queue length. Responding to a determination that the pending queue exceeds the maximum ordered queue length, the I/O device driver adds the I/O request based on a high pointer, and points the high pointer to the I/O request.

Abstract: A method and apparatus for detecting a connection between a peripheral device and a host device is described.

Abstract: An enhanced migration descriptor migrates a plurality of source sub-pages in a large source page accessible by direct memory access devices. A splitter and selector are integrated into a configuration of a computer. Responsive to a request to migrate a large page containing the plurality of source sub-pages in the source page, the splitter divides a plurality of high order page numbers from a plurality of low order page numbers. The selector selects the high order page number of the large page and creates an enhanced migration descriptor comprising the high order page number and a size of the large page. The selector, by the enhanced migration descriptor, combines the low order page number for a sub-page with the destination address and size of the enhanced migration descriptor to migrate the large page and each of the plurality of sub-pages.

Abstract: A method for enhancing the memory bandwidth available through a memory module of a memory system is provided. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

Abstract: A technique reduces cost, complexity and/or power consumption of a memory system by including intelligence in a memory buffer circuit of the memory system. An apparatus includes a memory buffer circuit configured to selectively operate in one of a plurality of modes. In a first mode, the memory buffer circuit is configured to interface to a first type of memory device, is configured to enable an input circuit of the memory buffer circuit, and is configured to drive on a terminal of a memory interface of the memory buffer circuit a version of a signal received by the input circuit during a memory operation. In a second mode, the memory buffer circuit is configured to interface to the first type of memory device, is configured to disable the input circuit, and is configured to drive a signal on the terminal during the memory operation.

Abstract: A computer-implemented method, system and computer program product for managing USB ports on blades in a blade center are presented. A set of remotely-transmitted instructions causes a multiplexer to physically disconnect one or more selected USB ports on a blade. In one embodiment, the same one or more selected USB ports are also software-disabled by a USB software-based controller.

Abstract: A system and method for testing and calibrating a control unit including a microcontroller includes an influencing device and an adaptation unit. The adaptation unit includes a memory that can store at least part of a data of a data communication between the influencing device and the control unit. The memory can be read from and/or written to by the microcontroller of the control unit when the control unit is in an on state.

Abstract: An information storage device includes a storage that stores transfer data from an information processing device, the information storage device being removably connected to the information processing device, a switch unit that switches a data transfer mode of the information processing device in accordance with manipulation by a user, and a controller that controls the information processing device to transfer data in a mode in which data temporarily stored in a data storing area is transferred to the storage or in a mode in which data is transferred to the storage without being temporarily stored in the data storing area in accordance with the selection of the data transfer mode by the switch unit.

Abstract: Described are techniques for managing a wait queue in a system. A plurality of buckets associated with the wait queue are defined. Each of the plurality of buckets is associated with one of more queue depth values and one or more counters. For each received request for service, a current depth of the wait queue indicating a number of other requests included in the wait queue waiting to be serviced is determined, a bucket in accordance with the current depth of the wait queue is selected and information is recorded by updating said one or more counters of the bucket selected. The received request is placed in the wait queue if there is another request currently being serviced or if there is at least one other request currently in the wait queue.

Abstract: A memory device removably insertable into or otherwise removably connected to a plurality of host devices includes a first memory storing multimedia data. A first circuit portion of the memory device determines the host device capabilities when the memory device is connected to a host device and a second circuit portion feeds the multimedia data to the host device in a format compatible with the determined capabilities of the host device.

Abstract: Direct memory access (‘DMA’) in a hybrid computing environment that includes a host computer, an accelerator, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where DMA includes identifying, by the system level message passing module, a buffer of data to be transferred from the host computer to the accelerator according to a DMA protocol; segmenting, by the system level message passing module, the buffer of data into a predefined number of memory segments; pinning, by the system level message passing module, the memory segments against paging; and asynchronously with respect to pinning the memory segments, effecting, by the system level message passing module, DMA transfers of the pinned memory segments from the host computer to the accelerator.

Abstract: A storage system includes a host and a storage apparatus. The host having multiple paths connecting with the storage apparatus transfers path identification information received from the storage apparatus, to the storage apparatus via all paths other than a path through which the path identification information has been transmitted. The storage apparatus includes a table for storing the path identification information transmitted to the host and path tables for storing the path identification information received from the host. When the storage apparatus receives a request for replacing the firmware, it determines whether the path tables are matched by comparing the path tables with each other. If the path tables are matched, the storage apparatus sequentially replaces the firmware corresponding to the multiple paths in a hot swapping manner.

Abstract: To provide a transceiving technology that controls the mounting area of a circuit pertaining to transmission and/or reception and where the utilization efficiency of a buffer is improved. In a transmission side circuit, there are disposed a transmission side first circuit component that generates a first packet that follows a request and a transmission side second circuit component that is a lower-level circuit component of the transmission side first circuit component, includes a transmission buffer and temporarily stores in the transmission buffer, and transmits, a second packet that includes the first packet. The second packet includes a second header portion and a second data portion. In the second data portion that the second packet that is transmitted from the transmission side second circuit component includes, there is included the first packet, and in the second header portion, there is included a predetermined value as a parameter value that represents the type of the second packet.

Abstract: A method for controlling power consumption of a Universal Serial Bus (USB) Mass Storage is provided. The USB Mass Storage is electrically connected to a USB port. The method includes: monitoring at least one Test Unit Ready (TUR) command from an operating system (OS) to the USB Mass Storage; and when it is detected that there is no other command from the OS to the USB Mass Storage for a predetermined time period, controlling the USB port to enter a suspend mode in order to save power supplied to the USB Mass Storage. An associated personal computer and a storage medium storing an associated USB Mass Storage driver for controlling power consumption of the USB Mass Storage are further provided, where the personal computer includes the storage medium. In particular, when the USB Mass Storage driver is executed by the personal computer, the personal computer operates according to the method.

Abstract: The present invention provides methods and apparatus for transferring and storing data among processors and memory in a multiprocessor system. The data is compressed locally before it is sent to a shared memory. The memory stores the data in its compressed state, but the data is aligned in the memory in the same manner as uncompressed data would be. A tag table keeps track of the compression type and compressed data size for a set of data at a given address block. A data compressor and a data expander may be implemented in a direct memory access controller accessible to multiple coprocessors, or the compressor and the expander may be implemented within the coprocessors.