Abstract: A data packer of an input/output hub of a computer system packs and formats write data that is supplied to it before the write data is written into a memory unit of the computer system. More particularly, the data packer accumulates write data received from lower bandwidth clients for delivery to a high bandwidth memory interface. Also, the data packer aligns the write data, so that when the write data is read out from the write data packer, no further alignment is needed.

Abstract: In an embodiment, a peripheral component configured to control an external interface of an integrated circuit. For example, the peripheral component may be a memory interface unit such as a flash memory interface unit. The internal interface to the peripheral component may be shared between data transfers to/from the external interface and control communications to the peripheral component. The peripheral component may include a command queue configured to store a set of commands to perform a transfer on the interface. A control circuit may be coupled to the command queue and may read the commands and communicate with an interface controller to cause a transfer on the interface responsive to the commands. In an embodiment, a macro memory may store command sequences to be performed in response to a macro command in the command queue. In an embodiment, an operand queue may store operand data for use by the commands.

Abstract: Reusing system configuration information and metadata for related operations is disclosed. It is determined that a group of content management system commands may be treated as a related set for purposes of updating content management system configuration information and/or metadata. The content management system configuration information and/or metadata are updated once for purposes of processing the group.

Abstract: There is described a method and system for inputting/outputting multiple data streams of variable widths. Input/output pins are grouped together via a plurality of transfer blocks, each transfer block being controlled by an independent clock. Data streams can therefore be input/output using asynchronous clocks. Two data streams can also be input/output on a single pin using the rising and falling edge of the clock.

Abstract: There is described a method and system for inputting/outputting multiple data streams of variable widths. Input/output pins are grouped together via a plurality of transfer blocks, each transfer block being controlled by an independent clock. Data streams can therefore be input/output using asynchronous clocks. Two data streams can also be input/output on a single pin using the rising and falling edge of the clock.

Abstract: An computer program product, apparatus, and method for facilitating input/output (I/O) processing for an I/O operation at a host computer system configured for communication with a control unit. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes the host computer system obtaining a transport command word (TCW) for an I/O operation. The TCW specifies a location of one or more I/O commands and a flag. The flag is set to indicate that the location is an indirect address. The host computer system extracts the location of the one or more I/O commands and the flag from the TCW. The host computer system gathers the one or more I/O commands responsive to the location specified by the TCW and the flag, and then forwards the one or more I/O commands to the control unit for execution.

Abstract: A method, system, and medium for compressing systems management information in a historical data store. Dynamically determining the appropriate compression algorithm to apply based on the type of data being compressed and stored. As further input is received for any particular measurement, the appropriate compression algorithm will be automatically selected from the set of available compression algorithms or be defined by a user configuration parameter. The amount of historical data stored with the minimal amount of data loss is optimized by the system dynamically changing the compression algorithm used for the given input data over a particular time span. The system engineer is therefore presented with the pertinent information for monitoring, administrating and diagnosing system activities.

Abstract: An image processing apparatus is capable of communicating data with a plurality of external apparatuses attached to the image processing apparatus. Each of the external apparatuses includes an advisor that advises a user of access to the external apparatus. A display section displays information on the external apparatuses attached to the image processing apparatus. A selecting section selects a desired one external apparatus from among the plurality of external apparatuses displayed on said display section. A transmitter transmits an access command to the desired one external apparatus. When the selected external apparatus receives the access command, the advisor advises the user of the access to the selected external apparatus, emitting flashing light.

Abstract: An on-vehicle electronic control device 100A serially transmits A/D conversion data of plural channels from a second control circuit unit 300A including a multichannel A/D converter 204A to a microprocessor 110A disposed in a first control circuit unit 200A. The A/D conversion data are organized into a communication packet and transmitted via first and second buffer memories 204b and 204d, and when there is an abnormality in the A/D conversion data, transfer between the first and second buffer memories 204b and 204d is prohibited and an abnormality report is performed with respect to the microprocessor 110A. As a result, erroneous data are not transmitted, and communication congestion and the burden of the microprocessor 110A are alleviated.

Abstract: Methods and apparatuses for processing input and/or output requests for data storage devices are disclosed. Method embodiments generally comprise receiving a number of requests, wherein at least one of the requests is an isochronous request having an initial deadline value, calculating a new deadline value for the isochronous request, and issuing the isochronous request when the new deadline value is less than a threshold value. Apparatus embodiments generally comprise a request receiver to receive a number input or output requests, a logic module to calculate a deadline value for an isochronous request, where the calculated deadline value relates to the amount of time which has transpired between the creation of the isochronous request and the time the calculation is made, and an issuance module to issue the isochronous request if the calculated deadline value is equal or less than a threshold value.

Abstract: A method of transmitting data on a data line between a central control device and a decentralized data processing device. During a normal operation of the system, the central control device periodically sends synchronization pulses to the at least one data processing device via the data line in order to request data packets, and the decentralized data processing device sends the data thereof to be transmitted, as data packets, to the central control device, following the synchronization pulse. The data line is embodied as a data bus. Each of the decentralized data processing devices is configured by the central control device before the first transmission of data packets to the central control device. In order to configure the system, a bi-directional communication is carried out between the central control device and the at least one decentralized data processing device.

Abstract: A method for data distribution, including distributing logical addresses among an initial set of devices so as provide balanced access, and transferring the data to the devices in accordance with the logical addresses. If a device is added to the initial set, forming an extended set, the logical addresses are redistributed among the extended set so as to cause some logical addresses to be transferred from the devices in the initial set to the additional device. There is substantially no transfer of the logical addresses among the initial set. If a surplus device is removed from the initial set, forming a depleted set, the logical addresses of the surplus device are redistributed among the depleted set. There is substantially no transfer of the logical addresses among the depleted set. In both cases the balanced access is maintained.

Abstract: A multi-protocol interface for coupling a field device to a general purpose computer is disclosed. The interface includes measurement circuitry to perform a plurality of measurements on a connected process communication loop to determine a process communication loop type. Then, if the interface includes a protocol interface module that matches the detected loop type, the protocol interface module can be engaged. A method for coupling a field device to a general purpose computer is also provided. In one aspect, power from the general purpose computer is used to power the process communication loop, if the interface determines that the loop is not powered.

Abstract: A peripheral device, with first and second communication conductors, is connectable to a computer having one of a first interface and a second interface. The first interface communicates with the peripheral device over a differential data connection having a first data conductor and a second data conductor. The second interface communicates with the peripheral device over a clock conductor and a single ended data connection which includes a data conductor. The peripheral device includes an interface detection component coupled to the first and second communication conductors to detect which of the first and second interfaces the peripheral device is connected to.

Abstract: A flexible input/output controller logic interfaces with existing input/output controllers (IOC's) in order to configure the amount of data sent to and received from the IOC's. The flexible I/O interface receives data from a component at a rate determined by the particular component. The flexible I/O interface then feeds the received data to a traditional I/O controller at a rate suitable for the I/O controller. Thus, the interface to the individual I/O controllers is maintained. The flexible I/O logic balances bandwidth between a plurality of individual I/O controllers in order to better utilize the overall system I/O bandwidth. In one embodiment, the I/O configuration managed by the flexible I/O logic is determined during system-build, while in another embodiment, the I/O configuration is set during system initialization.

Abstract: A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.

Abstract: A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.

Abstract: Mechanisms for enabling both native and non-native input/output virtualization (IOV) in a single I/O adapter are provided. The mechanisms allow a system with a large number of logical partitions (LPARs) and system images to use IOV to share a native IOV enabled I/O adapter or endpoint that does not implement the necessary number of virtual functions (VFs) for each LPAR and system image. A number of VFs supported by the I/O adapter, less one, are assigned to LPARs and system images so that they may make use of native IOV using these VFs. The remaining VF is associated with a virtual intermediary (VI) which handles non-native IOV of the I/O adapter. Any remaining LPARs and system images share the I/O adapter using the non-native IOV via the VI. Thus, any number of LPARs and system images may share the same I/O adapter or endpoint.

Abstract: Systems and methods for accessing host bus adapter (HBA) management features for Small Computer System Interface (SCSI) based HBAs produced by different vendors use a standard interface. A virtual SCSI target is created to emulate each HBA in a system, representing the HBA as a logical unit. Standard commands specified for logical units are used by an HBA device driver to perform HBA management operations. The standard commands may be used to access HBA management features for any HBA regardless of the vendor. Therefore, the HBA communication interface is standardized for HBA devices, permitting efficient access regardless of the operating system or HBA vendor.

Abstract: An interface to transfer data between a host processor and an external coprocessor is provided. The interface may operate in several write modes, in which in a first write mode the write operation is transferred across the interface in two clock cycles and in a second write mode the write operation is transferred across the interface in a single clock cycle. The interface can perform a first read operation initiated by the host processor and a second read operation initiated by the external coprocessor. The interface can include buffers to store read and write operations and clock gates to selectively gate off clock signals provided to the buffers to synchronize transfer of data into and out of the buffers. A selectable priority scheme can be modified to select between priorities that control a preference in transferring operations over the interface when both read and write operations are queued for transfer.