Abstract: A fluid infusion system as described herein includes a number of local “body network” devices, such as an infusion pump, a handheld monitor or controller, a physiological sensor, and a bedside or hospital monitor. The body network devices can be configured to support communication of status data, physiological information, alerts, control signals, and other information between one another. In addition, the body network devices can be configured to support networked communication of status data, physiological information, alerts, control signals, and other information between the body network devices and “external” devices, systems, or communication networks. The networked medical devices are configured to support a variety of wireless data communication protocols for efficient communication of data within the medical device network.

Abstract: A computer implemented method, data processing system, and computer program product for detecting circular buffer overflow. When an entry in the circular buffer is read, a valid mark bit in the entry is set to an inactive state and the location of the entry is stored as an entry previously processed. A valid mark bit of a next entry and the valid mark bit in the entry previously processed are read. Responsive to determining that the valid mark bit in the entry previously processed is in the inactive state and the valid mark bit in the next entry is in an active state, the next entry is read, the valid mark bit in the next entry is set to an incactive state, and the location of the next entry is stored as the entry previously processed. Responsive to determining that the valid mark bit in the entry previously processed is in the active state, a determination is made that a circular buffer overflow has occurred.

Abstract: An apparatus, a method, and a system for controlling communications between a host device and a USB device. The apparatus includes a controller to perform an operation for communication between a first device and a second device, and a first processor to selectively stop the operation of the controller according to information indicating a status of the communication between the first device and the second device. Thus, the USB device can perform a unique function even when the USB device is connected to the host via USB.

Abstract: An image processing apparatus includes a data bus provided to access a memory, a compressing unit which compresses an image data and outputs a compressed image data, a write unit which writes the compressed image data into the memory via the data bus, a read unit which reads a compressed image from the memory via the data bus, a decompression unit which decompresses the compressed data read by the read unit, and a control unit which controls operations of the write unit and the read unit, based on an amount per unit time of the compressed image data outputted from the compressing unit, an amount per unit time of the compressed image data read from the memory and a degree of congestion of the data bus.

Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.

Abstract: An isolated highway addressable remote transfer (HART) interface with programmable data flow is provided. The isolated HART interface includes a HART channel having at least one pair of terminals configured to connect with a HART device via a current loop. The HART channel is programmable to have each pair of terminals assigned as a current loop input or a current loop output.

Abstract: A reconfigurable computing device includes a reconfigurable logical device of which a circuit logic can be changed based on configuration data, a storage part to store beforehand input-output attributes of input-output parts of the reconfigurable logical device, and a verification part to verify the configuration data by making a comparison between information on the input-output parts in the configuration data and the input-output attributes stored in the storage part. With this, it is possible to inspect the configuration data of the reconfigurable logical device by a simple method.

Abstract: A key processing method for use in a computer system having at least one BIOS (basic input output system) and one controller is disclosed. The method comprises the following steps. After a predetermined time period, it is first determined whether a specific hotkey has been pressed. If so, the BIOS acquires identification data of the specific hotkey from the controller and performs a corresponding service.

Abstract: Methods and systems for improving communication throughput of a link between SAS/SATA devices. The link, initially established at a first signal rate, is one of a SATA link and a SAS link. A SAS/SATA device increments one of the at least one counter based on an error sensed on the link. Based on the at least one counter, the SAS/SATA device determines whether to maintain the first signal rate. The link is re-established at a second signal rate based on the determination such that the second signal rate is lower than the first signal rate.

Abstract: A semiconductor memory device includes a nonvolatile memory device having a plurality of physical sectors, and a memory controller configured to translate a logical address received from a host to a physical address, with reference to mapping data that defines a correspondence between the logical address and the physical address. The nonvolatile memory device is configured to access a first physical sector corresponding to the physical address, and, when a data delete command is provided from the host to the memory controller to delete first data that is stored in the first physical sector, the memory controller delays an erase and/or merge operation for the first physical sector in which the first data is stored.

Abstract: A communications device includes a communications circuit, a memory, an identifier generator, and a latency controller. The communications circuit exchanges serial data with a host computer and a downstream device, and includes a first input, a first output, a second input, and a second output. The first input receives data from the host computer. The first output transmits data to the host computer. The second input receives data from the downstream device. The second output transmits data to the downstream device. The memory is accessible through the communications circuit. The identifier generator generates an identifier number unique to the communications device in response to an identifier setup request received at the first input. The latency controller determines, based on the generated identifier number, a period of latency required to access the memory through the communications circuit.

Abstract: There is described a method, a bus protocol, a peripheral module, a processing unit, a hub and also to a system consisting of said components, for event signaling between at least one peripheral module and a processing unit by means of a system bus. In this case the data to be transmitted data is encoded into a larger symbol space, from which a standard idle symbol is used in telegram pauses for synchronizing a connection between transmitter and receiver. A message present at the peripheral modules is enabled to be signaled to the processing unit independently of the telegram traffic initiated by the processing unit.

Abstract: A physical layer device for interfacing with multiple computing devices includes a digital core and first and second analog front ends. The digital core is operative to perform one or more functions of the physical layer device. Each of the first and second analog front ends is operative to perform signal conversion between a digital domain and an analog domain. The physical layer device further includes a digital switching circuit coupled to the digital core and to the first and second analog front ends. The digital switching circuit is operative to electrically connect the digital core to the first analog front end or the second analog front end as a function of a control signal applied to the digital switching circuit.

Abstract: An apparatus and a method for processing high speed data using hybrid Direct Memory Access (DMA) are provided. The method includes determining a size of data to be transmitted, determining a memory access method of the data by comparing the determined size of the data with a first threshold, and determining an I/O bus access method of the data by comparing the determined size of the data with a second threshold.

Abstract: Devices in a process control system communicate by data messages over a communication medium segment. Each device includes a communication controller that includes a data queue and a queue of received message objects. The data queue stores a plurality of messages received on the communication medium. The received message objects contain information about a corresponding message in the data queue.

Abstract: An apparatus, system, and method are disclosed for converting a synchronous interface into an asynchronous interface. The apparatus includes a receive module, a generate module, and a return module. The receive module receives a request for a transaction from a synchronous requester, the generate module generates a delaying object and a forwarding interface compatible with the requested return type, and the return module returns the delaying object with the forwarding interface to the requester. Additionally, services for implementing such an apparatus, system, and method are disclosed. Implementation of the apparatus, system, and method provide for increased computing performance, reduced application run time, and decreased usage of computing resources.

Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.

Abstract: An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage.

Abstract: An apparatus and a process for transferring packet data includes receiving packets from a first interface such as a network interface and transferring data to a second interface such as an SD Bus interface such as SDIO using a protocol such as one described in SDCard.org. The SD Bus second interface operates as a slave device to a master device, and the packet transfer from first interface to second interface includes concatenating length fields and packet data fields from packets received on the first interface to form a superframe which is provided to the second interface at time of data transfer. The formation of each superframe includes starting a timer such that the superframe is transmitted to the second interface by asserting an interrupt on that interface when either the timer expires, the number of packet from the first interface exceeds a threshold, or the amount of data from the first interface exceeds a threshold.

Abstract: Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of requests which may be issued to a data storage device, assigning a completion deadline an isochronous request, and communicating the isochronous request and completion deadline information to the data storage device. Apparatus embodiments generally comprise a request identifier to identify an isochronous request, a logic module to assign a completion deadline to the isochronous request, and a communication module to communicate the isochronous request and the completion deadline to a data storage device. Alternative apparatus embodiments may include a monitor module to monitor a system process operating in the system and determine if the system process issues isochronous requests.