Abstract: One example method of testing an electrical device comprises transmitting a data pattern to a memory device of the electrical device by a controller of the electrical device to provide a written data pattern to the memory device, wherein the data pattern replicates a resonant frequency of at least a portion of the electrical device, reading the written data pattern from the memory device with the controller, and comparing the written data pattern to the data pattern.

Abstract: An example non-transitory computer readable storage medium comprising instructions that when executed cause a processor of a computing device to: in response to a trigger of a system management mode (SMM), verify all processor threads have been pulled into the SMM; in response to a successful verification, enable write access to a non-volatile memory of the computing device via two registers, where the writing access is disabled upon booting of the computing device; and upon exiting the SMM, disable the write access via the two registers.

Abstract: An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a deallocation command corresponding to a plurality of deallocation requests, where each of the plurality of deallocation requests corresponds to a logical block address (LBA) range, determine that at least one of the plurality of deallocation requests is an unaligned deallocation request, generate a tag for metadata for the unaligned deallocation request, wherein the tag for the metadata includes a direction bit and a length bit, concatenate the metadata including the tag to an LBA range of the unaligned deallocation request, and complete the deallocation command using the metadata including the tag. Aligned deallocation requests are stored in a buffer. The concatenated unaligned deallocation requests are completed prior to completing the aligned deallocation requests from the buffer.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a host configured to generate and output a host command and a host address and to receive and store host map data, a controller configured to store map data, generate an internal command in response to the host command, and map the host address to an internal address based on the map data, and a memory device configured to perform an operation in response to the internal command and the internal address, wherein the controller is configured to load, when the map data corresponding to the host address is not stored in the controller, new map data into a map data storage area storing map data that is identical to the host map data.

Abstract: A memory profiling system can generate profiles for target memory units of a memory component during runtime of the memory component. The memory profiling system can identify target memory units based on trigger conditions such as memory units crossing a specified depth in error recovery, receipt of a vendor specific (VS) command, memory unit retirement, or excessive background scan rates. In some cases, the memory profiling system can identify additional target memory units that are related to identified target memory units. The characterization processes can include computing voltage threshold (vt) distributions, Auto Read Calibration (ARC) analysis, Continuous Read Level Calibration (cRLC) analysis, DiffEC metrics, or gathering memory component metrics. The memory profiling system can store the generated profiles and can utilize the generated profiles to adjust operating parameters of one or more memory elements of the memory device, in real time.

Abstract: Examples described herein relate to In some examples, a least recently used (LRU) list used to evict nodes from a cache is traversed, the nodes referencing data blocks storing data in a storage device, the nodes being leaf nodes in a tree representing a file system, and for each traversed node, determining a stride length as an absolute value of a difference between a block offset value of the traversed node and a block offset value of a previously traversed node, comparing the stride length to a proximity threshold, and updating a sequential access pattern counter based at least in part on the comparing; and proactively prefetching nodes from the storage device to the cache when the sequential access pattern counter indicates a detected pattern of sequential accesses to nodes.

Abstract: A system and method for reordering data blocks received from a zone of a memory device. An example method includes sending, by a host system to a memory sub-system comprising a memory device, a plurality of write commands; receiving, by the host system from the memory sub-system, block allocation metadata, wherein the block allocation metadata references one or more locations in the memory device corresponding to a zone; generating, by the host system, a reorder map based on the block allocation metadata; reading a plurality of data blocks associated with the zone; and reordering, by the host system, the plurality of data blocks based on the reorder map.

Abstract: An input/output (I/O) write request directed at a plurality of memory devices having memory cells is received by a processing device. The write request includes a set of data. The processing device appends the set of data to a compound data object. The compound data object comprises one or more sequentially written data objects. The processing device associates the compound data object with one or more groups of memory cells of the plurality of memory devices. The processing device causes the compound data object to be written to the one or more groups of memory cells of the plurality of memory devices.

Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: calculating an overall spare area in a flash memory, which includes a spare area in a plurality of spare blocks in the flash memory and at least two of a spare area in one or more target blocks corresponding to writing of user data based on host write commands, a spare area in one or more destination blocks corresponding to writing of valid data based on the GC operation and a spare area in a source block corresponding to reading of valid data based on the GC operation; determining an adjustment factor according to the overall spare area; and performing the GC operation on the source block according to a GC-to-host base ratio and the adjustment factor.

Abstract: In an embodiment, a system includes a plurality of memory components that each include a plurality of management groups. Each management group includes a plurality of sub-groups. The system also includes a processing device that is operatively coupled with the plurality of memory components to perform wear-leveling operations that include maintaining a sub-group-level delta write count (DWC) for each of the sub-groups of each of the management groups of a memory component in the plurality of memory components. The wear-leveling operations also include determining, in connection with a write operation to a first sub-group of a first management group of the memory component, that a sub-group-level DWC for the first sub-group equals a management-group-move threshold, and responsively triggering a management-group-move operation from the first management group to a second management group of the memory component.

Abstract: An electronic device includes a NAND flash memory device, a memory controller that issues a command for performing either erasing or writing of data to the NAND flash memory device, and a voltage monitor that monitors a power supply and detects a voltage drop. When the voltage drop is detected before an issue of the command, the memory controller ceases the issue of the command to the NAND flash memory device.

Abstract: In a log based system, a reclamation list of cache pages containing dirty data can be maintained and used. The cached dirty data pages identified by the reclamation list can be candidates for eviction from the cache. A cached dirty data page on the reclamation list can be persistently logged in a transaction log extension having storage allocated from a non-volatile solid state drive (SSD). The reclamation list can include descriptors of the cached dirty data pages prioritized for eviction in accordance with a least recently used (LRU) policy so that the LRU cached dirty data page can be selected for eviction. When a dirty data page which was evicted from the cache is reloaded into cache, the dirty data page can be added to the reclamation list by adding its page descriptor to the reclamation list. A dirty data page can be removed from the reclamation list once flushed.

Abstract: The present invention aims to specify a bottlenecked resource more accurately in an IT system. In a performance analysis apparatus which includes a processing device, a storage device and an input/output interface and analyzes a performance of an IT system, the processing device creates an overall performance prediction model by using a nonlinear regression algorithm with a first overall performance value being set as an objective variable and with a first resource performance value being set as an explanatory variable, creates an explanatory model by inputting the overall performance prediction model and using an XAI technology and calculates a degree of per-resource influence on the overall performance value which is output by inputting a second resource performance value into the explanatory model.

Abstract: A memory controller includes: a map cache area for storing a map cache lines including mapping information between a logical address and a physical address; a victim map cache line selector for selecting a victim map cache line among the map cache lines, using a victim map cache line selection model trained by using a storage state information as training data, when a physical address corresponding to a logical address of an operation request is absent in the map cache area; and a map data controller for removing the selected victim map cache line from the map cache area, providing the removed victim map cache line to a memory device, receiving a target map cache line including the physical address corresponding to the logical address of the operation request from the memory device, and storing the target map cache line in the map cache area.

Abstract: A system includes integrated circuit (IC) dice having memory cells and a processing device coupled to the IC dice. The processing device is to perform operations including: causing a logic to enter an initial state associated with a first group of memory cells in response to an input-output (IO) write request directed at the first group of memory cells; retrieving a write pointer that includes a location within the first group of memory cells; causing the logic to transition from the initial state to a sequential IO state; and in response to determining the IO write request is directed to the location of the write pointer, causing data of the IO write request to be written to the plurality of IC dice starting at the location of the write pointer.

Abstract: Embodiments described herein provide improved methods and systems for generating metadata for media objects at a computational engine (such as an artificial intelligence engine) within the storage edge controller, and for storing and using such metadata, in data processing systems.

Abstract: Embodiments of the present disclosure provide a protective apparatus for an indirect access memory controller. The apparatus can include: a bus monitoring unit configured to monitor a bus address and detect an operation type of a bus accessing the indirect access memory controller, update a corresponding window register if the operation type is a window register operation, initiate permission authentication if the operation type is a register controlling operation, and perform list entry configuration if the operation type is a permission list configuration operation; a window register unit configured to store operation addresses of different access types; a permission list unit configured to partition a memory space into several virtual memory protection areas, and independently set a access permission attribute for each memory area; and an unauthorized operation processing unit configured to process a subsequent operation performed when a permission violating access occurs.

Abstract: According to one embodiment, a memory circuit includes a plurality of nonvolatile memory cells and a control circuit. Each of the plurality of nonvolatile memory cells loses stored data when the stored data is read. The control circuit reads data from a first memory cell among the plurality of memory cells as designated by a first instruction but does not write the data read from the first memory cell back to the first memory cell after the first instruction is received. The control circuit reads data from a second memory cell among the plurality of memory cells as designated by a second instruction and writes the data read from the second memory cell back to the second memory cell after the second instruction is received.

Abstract: A file reading method includes following operations: determining, by a processor, whether a file in a SIM card is stored in a non-volatile memory; performing, by the processor, a reading process to read the file from the SIM card if the file is not stored in the non-volatile memory; and storing, by the processor, the file into the non-volatile memory.