Abstract: A storage apparatus includes: a memory that stores data and main management information, the main management information identifying a physical address of the data; and processing circuitry configured to generate preliminary management information that includes information of the same content as the main management information, and select, as use management information, any one of the main management information and the preliminary management information upon start of the storage apparatus. Access to the data stored in the memory is performed using the selected use management information.

Abstract: A method of managing a garbage collection (GC) operation includes: comprising: selecting a source block and at least one candidate source block from the flash memory; calculating an overall valid page percentage according to a number of valid pages in the source block and the at least one candidate source block; determining a GC-to-host base ratio according to the overall valid page percentage; and performing the GC operation on the source block according to at least the GC-to-host base ratio.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.

Abstract: A method performed by a slave device to obtain a host memory address includes: inquiring a description list to obtain information of an allocated memory of a host; dividing the allocated memory into N storage spaces according to the information; using a first memory space of the N storage spaces to store a first level look-up table indicating physical addresses of the N storage spaces; dividing the first memory space into M storage spaces; storing a second level look-up table in the slave device to indicate physical addresses of the M storage spaces; inquiring the second level look-up table according to a logical address and obtaining a first index indicating a physical address of one of the M storage spaces; and inquiring the first level look-up table according to the first index and obtaining a second index indicating a physical address of one of the N storage spaces.

Abstract: A method of managing a storage system comprises detecting a reference to a first page in the storage system. The method also comprises creating a first candidate block for the first page based on the detecting. The first candidate block may comprise a continuous series of pages that begins with the first page. The method also comprises monitoring subsequent references to pages within the first candidate block. The method also comprises determining that the first candidate block meets a first set of hot-block requirements. The method also comprises relocating the first candidate block to a hot-block space in a buffer pool based on the determining, resulting in a first hot block.

Abstract: A storage device includes: a memory device including a map data block including mapping information between a logical address and a physical address; a buffer memory device for storing a block state table including block state information; and a memory controller for determining valid data of a source block among the plurality of memory blocks based on mapping information and block state information corresponding to the source block, and moving the valid data to open memory block. The memory controller may generate a valid page list in which information of the valid data is arranged in a stripe page unit according to an order of logical addresses, and control the memory device to move the valid data to the open memory block, based on the valid page list.

Abstract: Methods, systems, and devices for session-based memory operation are described. A memory system may determine that a logical address targeted by a read command is associated with a session table. The memory system may write the session table to a cache based on the logical address being associated with the session table. After writing the session table to the cache, the memory system may use the session table to determine one or more logical-to-physical (L2P) tables and write the one or more L2P tables to the cache. The memory system may use the L2L tables to perform address translation for logical addresses.

Abstract: Various embodiments set forth techniques for transactional allocation and deallocation of blocks in a block store. A first technique includes sending a first request that causes a non-persistent allocation of a block. The first technique also includes adding a first entry in a log recording the allocation as tentative, sending a second request that causes persistence of the allocation, and adding a second entry in a log recording the allocation as finalized. A second technique includes adding a first entry in a log recording a deallocation of a block, sending a first request that causes the deallocation of the block and causes the block to be unavailable for reallocation in a non-persistent manner, adding a second entry in the log recording that the deallocation is finalized, and sending a second request that causes the block to be made available for reallocation.

Abstract: A non-volatile storage device according to an embodiment of the present technology includes a storage section and a calculation section. The storage section includes a plurality of block sections each including a plurality of page sections into which data can be written independent of each other, the plurality of block sections being capable of collectively deleting the data written in the plurality of page sections. The calculation section calculates, on the basis of information about write conditions of the plurality of page sections included in the storage section, candidate addresses that are candidates of logical addresses of the data to be written into the plurality of page sections.

Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.

Abstract: An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory.

Abstract: An example apparatus comprises a controller coupled to a non-volatile memory (NVM) device. The controller may be configured to cause a logical block address (LBA) to be stored in a first logical-to-physical (L2P) data structure in the NVM device and a physical block address (PBA) to be stored in a second L2P data structure in the NVM device The first L2P data structure and the second L2P data structure may have a same size associated therewith.

Abstract: A predictive method for scheduling of the operations is described. The predictive method utilizes data generated from computing an expected lifetime of the individual files or objects within the container. The expected lifetime of individual files or objects can be generated based on machine learning techniques. Operations such as garbage collection are scheduled at an epoch where computational efficiencies are realized for performing the operation.

Abstract: Various embodiments described herein provide for operation of a memory sub-system based on a profile (also referred to herein as an operational profile) that causes the memory sub-system to have a specific set of operational characteristics. Additionally, some embodiments can provide dynamic switching between profiles based on a set of conditions being satisfied, such as current time of day or detection of a particular data input/out (I/O) pattern with respect to the memory sub-system.

Abstract: The present technology relates to an electronic device. A storage device includes a memory device including pages, a buffer memory configured to store address mapping information including a mapping relationship between logical addresses provided from a host and physical addresses corresponding to the pages, first trim bitmap information including trim information of first logical address groups each including a first number of logical addresses having at least two of the logical addresses, and second trim bitmap information including trim information of second logical address groups each including a second number of logical addresses greater than the first number of the logical addresses, and a memory controller configured to change, based on a number of trim-requested logical addresses from the host, map states of the trim-requested logical addresses in one of the address mapping information, the first trim bitmap information, and the second trim bitmap information.

Abstract: Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.

Abstract: A method, a computer program product, and a system for allocating a variable into storage class memory during compilation of a program. The method includes selecting a variable recorded in a symbol table during compilation and computing a variable size of the variable by analyzing attributes related to the variable. The method further includes computing additional attributes relating to the variable. The method also includes computing a control flow graph and analyzing the control flow graph and the additional attributes to determine an allocation location for the variable. The method further includes allocating the variable into a storage class memory based on the analysis performed.

Abstract: A memory system may transfer a reference write size for a memory device to a host, and, when receiving, from the host, a write request for first data having a size corresponding to a multiple of the reference write size, may directly write the first data to the memory device without caching the first data in a write cache.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device and a memory controller. The memory device may include first memory blocks and second memory blocks. The memory controller may be configured to control the memory device so that valid data stored in a victim block, among the first memory blocks, is stored in a target block, among the second memory blocks, based on a result of a comparison between an amount of valid data stored in the victim block and a reference value. Each of the first memory blocks may include memory cells each configured to store n bits, where n is a natural number of 2 or more. Each of the second memory blocks may include memory cells each configured to store m bits, where m is a natural number less than n.