Abstract: A group III nitride semiconductor light emitting device including an LED structure formed on top of a single crystal, base layer (103) formed on top of a substrate (101) including a principal plane (10) having a flat surface (11) configured from a (0001) C plane, and a plurality of convex portions (12) including a surface (12c) non-parallel to the C plane having a width (d1) of 0.05 to 1.5 ?m and height (H) of 0.05 to 1 ?m, the base layer is formed by causing a group III nitride semiconductor to grow epitaxially so as to cover the flat surface and convex portions, and the width (d1) of the convex portions and top portion thickness (H2) of the base layer at the positions of the top portions (12e) of the convex portions satisfy: H2=kd1 (wherein 0.5<k<5, and H2=0.5 ?m or more).

Abstract: A pressure loss section H1 (H2) extends from a position corresponding to a corner of a resin package, and S1 is the minimum value of the opening area of the pressure loss section H1 (H2) perpendicular to the direction of resin flow (X axis) in the pressure loss section H1 (H2) during resin molding, while S2 is the average value of the opening areas of excess resin reservoirs H3 to H5 perpendicular to the direction of resin flow (Y axis) within excess resin reservoir H3 to H5 during molding. In this lead frame, S1<S2 is satisfied.

Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.

Abstract: Some embodiments include photonic systems. The systems may include a silicon-containing waveguide configured to direct light along a path, and a detector proximate the silicon-containing waveguide. The detector may comprise a detector material which has a lower region and an upper region, with the lower region having a higher concentration of defects than the upper region. The detector material may comprise germanium in some embodiments. Some embodiments include methods of forming photonic systems.

Abstract: In one embodiment, a power transistor device comprises a substrate that forms a PN junction with an overlying buffer layer. The power transistor device further includes a first region, a drift region that adjoins a top surface of the buffer layer, and a body region. The body region separates the first region from the drift region. First and second dielectric regions respectively adjoin opposing lateral sidewall portions of the drift region. The dielectric regions extend in a vertical direction from at least just beneath the body region down at least into the buffer layer. First and second field plates are respectively disposed in the first and second dielectric regions. A trench gate that controls forward conduction is disposed above the dielectric region adjacent to and insulated from the body region.

Abstract: A tape adhesive type material is directionally conductive. According to an example embodiment of the present invention, carbon nanotubes (212, 214, 216, 218) are configured in a generally parallel arrangement in a tape base type material (210). The carbon nanotubes conduct (e.g., electrically and/or thermally) in their generally parallel direction and the tape base type material inhibits conduction in a generally lateral direction. In some implementations, the tape base material is arranged between integrated circuit components (220, 230), with the carbon nanotubes making a conductive connection there between. This approach is applicable to coupling a variety of components together, such as integrated circuit dies (flip chip and conventional dies) to package substrates, to each other and/or to leadframes.

Abstract: A first memory device and second memory device have a same input/output layout configuration. To form a stack, the second memory device is secured to the first memory device. To facilitate connectivity, the second memory device is rotationally offset with respect to the first memory device in the stack to align outputs of the first memory device with corresponding inputs of the second memory device. The rotational offset of the second memory device with respect to the first memory device aligns one or more outputs of the first memory device with one or more respective inputs of the second memory device. Based on links between outputs and inputs from one memory device to another in the stack, the stack of memory devices can include paths facilitating one or more series connection configurations through he memory devices.

Abstract: A package structure including a circuit substrate, at least a chip, leads and an encapsulant is provided. The circuit substrate has a first surface, a second surface opposite to the first surface, and contacts disposed on the first surface. The chip is disposed on the second surface of the circuit substrate and electrically connected to the circuit substrate. The leads are disposed on the periphery of the second surface and surround the chip. Each lead has an inner lead portion and an outer lead portion and is electrically connected to the circuit substrate via the inner lead portion. The encapsulant encapsulates the circuit substrate, the chip and the inner lead portion and exposes the first surface of the circuit substrate and the outer lead portion, wherein the upper surface of the encapsulant and the first surface of the circuit substrate are coplanar with each other.

Abstract: According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers, barrier layers, and a well layer. The n-type and p-type semiconductor layers and the barrier layers include nitride semiconductor. The barrier layers are provided between the n-type and p-type semiconductor layers. The well layer is provided between the barrier layers, has a smaller band gap energy than the barrier layers, and includes InGaN. At least one of the barrier layers includes first, second, and third layers. The second layer is provided closer to the p-type semiconductor layer than the first layer. The third layer is provided closer to the p-type semiconductor layer than the second layer. The second layer includes AlxGa1?xN (0<x?0.05). A band gap energy of the second layer is larger than the first and third layers. A total thickness of the first and second layers is not larger than the third layer.

Abstract: A method of assembling a package includes aligning a pad chip with a spring chip to form at least one interconnect in an interconnect area, adhering the pad chip to the spring chip so that there is a gap between the pad chip and the spring chip, dispensing underfill material into the gap to seal the interconnect area from an environment external to the package, and curing the underfill material to form a solid mold.

Abstract: A semiconductor device includes a chip. The chip includes a single circuit element formed in a semiconductor substrate, a first metal layer on a first face of the semiconductor substrate, and a second metal layer on a second face of the semiconductor substrate opposite the first face. The first metal layer and the second metal layer are configured for accessing the single circuit element. A smaller of a first width of the first face of the semiconductor substrate and a second width of the first face of the semiconductor substrate perpendicular to the first width is less than or equal to a distance between an exposed face of the first metal layer parallel to the first face of the semiconductor substrate and an exposed face of the second metal layer parallel to the second face of the semiconductor substrate.

Abstract: A method and apparatus for placing quartz SAW (Surface Acoustic Wave) devices together with a clock/oscillator have been disclosed. Mounting on a single lead frame both a SAW device and an integrated circuit (IC).

Abstract: An optoisolator leadframe assembly includes: an emitter leadframe part including a first rail and a plurality of emitter leadframe units, each rail including two rows of emitter leadframes, each having a die-mounting pad; and a receiver leadframe part including a second rail and a plurality of receiver leadframe units, each including two rows of receiver leadframes, each having a die-mounting pad. The die-mounting pads of the emitter leadframes of each row of each of the emitter leadframe units are respectively aligned with and spaced apart from the die-mounting pads of the receiver leadframes of an adjacent row of an adjacent one of the receiver leadframe units. Each of the emitter and receiver leadframe parts is a single piece.

Abstract: An object is to provide a light-emitting element in which suppression of a drive voltage increase is achieved. Another object is to provide a light-emitting device that has reduced power consumption by including such a light-emitting element. In a light-emitting element having an EL layer between an anode and a cathode, between the cathode and the EL layer, a first layer capable of carrier generation is formed in contact with the cathode, a second layer which accepts and transports the electrons generated in the first layer is formed in contact with the first layer, and a third layer which injects the electrons accepted from the second layer into the EL layer is formed in contact with the second layer.

Abstract: Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.

Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a lead frame including a major surface, and a die having including a bond pad. A wire may electrically couple a location of the major surface of the lead frame with the bond pad of the die, the wire being situated such that the wire is substantially unbent from the location of the major surface to an edge of the lead frame.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a dielectric layer, a pad structure and a protection structure. The dielectric layer is disposed on the substrate. The pad structure is disposed in the dielectric layer. The pad structure includes a plurality of first metal layers and a plurality of plugs which are electrically connected to each other vertically. There is no contact plug disposed between the pad structure and the substrate. The protection structure is disposed in the dielectric layer and encompasses the pad structure.

Abstract: A semiconductor structure. The semiconductor comprises a substrate, a first deep well, a diode and a transistor. The first deep well is formed in the substrate. The diode is formed in the first deep well. The transistor is formed in the first deep well. The diode is connected to a first voltage, the transistor is connected to a second voltage, and the diode and the transistor are cascaded.

Abstract: A pressure-contact power semiconductor module is arranged on a heat sink. The power semiconductor module is used with at least one substrate provided with conductor tracks and power semiconductor components. The module has a mounting body, on the underside of which the at least one substrate is arranged, and which is formed with cutouts. The module also includes a load connection element which is provided with contact feet that project away from strip sections and make pressure contact with the conductor tracks. The power semiconductor module additionally has a dimensionally stable cover, which covers the mounting body on all sides and is connected to the mounting body by means of snap-action latching connections. At least one pad element is restrained between the cover and the strip sections of the load connection elements.

Abstract: Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.