Patents Examined by Teresa M. Arroyo
  • Pillar bumps and process for making same
    Patent number: 8823166
    Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu
  • Semiconductor package and stacked semiconductor package having the same
    Patent number: 8823158
    Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jae Sung Oh, Moon Un Hyun, Jong Hyun Kim, Jin Ho Gwon, Dong You Kim, Ki Bon Cha
  • Stacked semiconductor package
    Patent number: 8791558
    Abstract: A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: July 29, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jin Ho Bae, Ki Young Kim, Jong Hyun Nam
  • Integrated circuit packaging system with leads and transposer and method of manufacture thereof
    Patent number: 8786063
    Abstract: A method of manufacture of an integrated circuit packaging system includes: conductively bonding a first surface of a transposer to an inner end of a lead separate from the transposer; conductively bonding a die to the first surface of the transposer; and encapsulating the inner end with a mold compound having a bottom mold surface that is exposed and is coplanar with a surface of the transposer opposite the first surface.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: July 22, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Arnel Senosa Trasporto
  • Field-effect transistor with nitride semiconductor and method for fabricating the same
    Patent number: 8779438
    Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a p-type GaN layer and a heavily doped p-type GaN layer are formed in this order. A gate electrode forms an Ohmic contact with the heavily doped p-type GaN layer. A source electrode and a drain electrode are provided on the undoped AlGaN layer. A pn junction is formed in a gate region by a two dimensional electron gas generated at an interface between the undoped AlGaN layer and the undoped GaN layer and the p-type GaN layer, so that a gate voltage can be increased.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: July 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Masahiro Hikita, Tetsuzo Ueda, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Semiconductor device with a semiconductor chip connected in a flip chip manner
    Patent number: 8754535
    Abstract: A semiconductor device (1,21) includes a solid state device (2,22), a semiconductor chip (3) that has a functional surface (3a) on which a functional element (4) is formed and that is bonded on a surface of the solid state device with the functional surface thereof facing the surface of the solid state device and while maintaining a predetermined distance between the functional surface thereof and the surface of the solid state device, an insulating film (6) that is provided on the surface (2a, 22a) of the solid state device facing the semiconductor chip and that has an opening (6a) greater in size than the semiconductor chip when the surface of the solid state device facing the semiconductor chip is vertically viewed down in plane, and a sealing layer (7) that seals a space between the solid state device and the semiconductor chip.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: June 17, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Kazumasa Tanida, Osamu Miyata
  • Package for housing semiconductor element and semiconductor device using the same
    Patent number: 8754519
    Abstract: According to one embodiment, a package for housing semiconductor element includes: a base plate including a top surface and a recessed portion formed as a downwardly-recessed portion of the top surface; a peripheral wall provided on the top surface of the base plate; a lid provided on an upper side of the peripheral wall and forming a semiconductor element housing space in cooperation with the base plate and the peripheral wall; and a feed-through terminal including a bottom end and fixed to the recessed portion so that the bottom end is located at a lower position than the top surface of the base plate except the recessed portion.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Hasegawa
  • Lead frame apparatus and method for improved wire bonding
    Patent number: 8754513
    Abstract: In one embodiment, the present invention includes a lead frame for accommodating a semiconductor die. The lead frame includes a die attach pad, a first plurality of conductive finger ends, and a second plurality of conductive finger ends. The first plurality of conductive finger ends are arranged within a first elongated region. This first elongated region is located along the first edge of the die attach pad. The second plurality of conductive finger ends is arranged within a second elongated region. The second elongated region has an end adjacent to an end of the first elongated region. The second elongated region is positioned at an angle that is greater than ninety degrees from the first elongated region.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: June 17, 2014
    Assignee: Marvell International Ltd.
    Inventor: Chender Chen
  • High power semiconductor package with conductive clip and flip chip driver IC with integrated control transistor
    Patent number: 8749034
    Abstract: One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventors: Eung San Cho, Chuan Cheah
  • Multi chip semiconductor device
    Patent number: 8736074
    Abstract: According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: May 27, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Daisuke Iguchi, Kanji Otsuka, Yutaka Akiyama
  • Radiation hardened FinFET
    Patent number: 8735990
    Abstract: The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Robert H. Dennard, Mark C. Hakey, Edward J. Nowak
  • Assembly of a wire element with a microelectronic chip with a groove comprising at least one bump securing the wire element
    Patent number: 8723312
    Abstract: The assembly comprises at least one microelectronic chip having two parallel main surfaces and lateral surfaces, at least one of the lateral faces comprising a longitudinal groove housing a wire element having an axis parallel to the longitudinal axis of the groove. The groove is delineated by at least two side walls. The wire element is secured to the chip at the level of a clamping area between at least one bump arranged on one of the side walls, and the side wall of the groove opposite said bump. The clamping area has a smaller height than the diameter of the wire element and a free area is arranged laterally to the bump along the longitudinal axis of the groove. The free area has a height, corresponding to the distance separating the two side walls, that is greater than the diameter of the wire element.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: May 13, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean Brun, Dominique Vicard, Sophie Verrun
  • Stacked wafer level package and method of manufacturing the same
    Patent number: 8704350
    Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: April 22, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim, Ju Pyo Hong, Hee Kon Lee, Hyung Jin Jeon, Jing Li Yuan, Jong Yun Lee
  • Nitride semiconductor light emitting device
    Patent number: 8674381
    Abstract: A nitride semiconductor light emitting device is provided with a substrate, an n-type nitride semiconductor layer, a p-type nitride semiconductor layer, an n-side pad electrode, a translucent electrode and a p-side pad electrode, wherein the translucent electrode is formed from an electrically conductive oxide, the n-side pad electrode adjoins the periphery of the translucent electrode and the p-side pad electrode is disposed so as to satisfy the following relationships: 0.3L?X?0.5L and 0.2L?Y?0.5L where X is the distance between ends of the p-side pad electrode and the n-side pad electrode, Y is the distance between the end of the p-side pad electrode and the periphery of the translucent electrode, L is the length of the translucent electrode on the line connecting the centroids of the p-side pad electrode and the n-side pad electrode minus the outer diameter d of the p-side pad electrode.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: March 18, 2014
    Assignee: Nichia Corporation
    Inventors: Takahiko Sakamoto, Yasutaka Hamaguchi
  • Semiconductor power module
    Patent number: 8648462
    Abstract: A semiconductor power module includes an active element and a passive element serving as semiconductor elements each having a first electrode on a front surface and a second electrode on a back surface thereof, a heat pipe having a first region defined as arrangement parts of the active element and the passive element on its one end side and electrically connected to one of the first and second electrodes of the active element and the passive element arranged in the first region, a cooling fin arranged in a second region defined on the other end side of the heat pipe, and a heat pipe provided to sandwich the active element, the passive element, and the cooling fin arranged on the heat pipe along with the heat pipe and electrically connected to the other of the first and second electrodes of the active element and passive element.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: February 11, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichi Ushijima
  • Stacked chip-on-board module with edge connector
    Patent number: 8633576
    Abstract: A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: January 21, 2014
    Assignee: Tessera, Inc.
    Inventors: Wael Zohni, Belgacem Haba
  • Fixture for semiconductor device and assembly of semiconductor device
    Patent number: 8629555
    Abstract: A pressing portion of a fixture is put on a lid of a semiconductor package, and anchor portions on the opposite sides of the pressing portion are opposed to a baseplate. Two screw members are passed individually through opening parts formed spanning the pressing portion and anchor portions and threadedly engage with a heat sink through the baseplate. If the screw members are tightened in this state, the anchor portions are pressed by the baseplate, and the pressing portion presses the lid of the semiconductor package, whereby the baseplate is fixed to the heat sink in pressure contact with it.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Hasegawa
  • Semiconductor device with wireless communication
    Patent number: 8619003
    Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Konami Izumi
  • Solder alloy and semiconductor device
    Patent number: 8598707
    Abstract: A solder alloy includes 5 to 15% by mass of Sb, 3 to 8% by mass of Cu, 0.01 to 0.15% by mass of Ni, and 0.5 to 5% by mass of In. The remainder thereof includes Sn and unavoidable impurities. Thereby, highly reliable solder alloy and semiconductor device suppressing a fracture in a semiconductor element and improving crack resistance of a solder material can be obtained.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: December 3, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akira Maeda, Kenji Otsu, Akira Yamada
  • Carbon nanotube-based interconnection element
    Patent number: 8598708
    Abstract: An element to interconnect at least two conductors of a microelectronic circuit is disclosed that includes an initial conductor, referred to as lower conductor; a dielectric layer situated on the initial conductor; a second conductor, referred to as upper conductor, on the dielectric layer; a cavity in the dielectric layer emerging, on the one hand, on the lower conductor and, on the other hand, on the upper conductor. The upper conductor forms a bridge above the lower conductor and the cavity forms, at a level where it emerges on the upper conductor, two vents on both sides of the latter.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: December 3, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean Dijon, Philippe Pantigny