Abstract: A layered chip package includes a main body, and wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of semiconductor chips stacked, and a plurality of electrodes that electrically connect the semiconductor chips to the wires. A method of manufacturing the layered chip package includes the steps of: fabricating a substructure that includes an array of a plurality of pre-separation main bodies and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are split into two sets of wires of two separate main bodies, whereby a plurality of layered chip packages are formed.

Abstract: A semiconductor chip includes a semiconductor chip body having a top surface, a bottom surface, and side surfaces. The bottom surface may have a groove pattern defined by removing a partial thickness of the semiconductor chip body to extend from one or more edges of the semiconductor chip body toward a center portion of the semiconductor chip body. Through electrodes may be formed to extend from the top surface of the semiconductor chip body and pass through the groove pattern defined on the bottom surface. A heat dissipation pattern may fill in the groove pattern defined on the bottom surface and may be connected with the through electrodes.

Abstract: In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.

Abstract: A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.

Abstract: Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

Abstract: A light-emitting diode package is provided. The light-emitting diode package comprises a substrate and a first metal layer disposed over the substrate. A solder layer is disposed on the first metal layer and a light-emitting diode chip is disposed on the solder layer, wherein the light-emitting diode chip comprises a conductive substrate and a multilayered epitaxial structure formed on the conductive substrate, and wherein the conductive substrate is adjacent to the solder layer.

Abstract: A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy?K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz?K2yy>K2xx or K2yy?K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.

Abstract: An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials.

Abstract: An integrated circuit assembly (ex.—a flip chip package, a wire bond chip package) is provided which includes a substrate (ex.—a printed circuit board) and a die assembly. The die assembly includes an integrated circuit chip which is connected to the printed circuit board. Further, an external dielectric layer (ex.—a solder mask layer) of the printed circuit board is at least substantially coated with a conductive coating (ex.—a low sintering temperature, nano-particle silver coating). The conductive coating is not in contact with the die assembly and/or passive electronics which are connected to the printed circuit board, however the conductive coating is electrically connected to the printed circuit board. The conductive coating provides (ex—acts as) an external ground plane for the printed circuit board.

Abstract: A three-dimensional semiconductor module and an electronic system including the same are provided. The semiconductor module includes a module substrate, a logic device formed on a part of the module substrate, and a plurality of memory devices formed on another part of the module substrate, wherein the plurality of memory devices are disposed perpendicular to the logic device, and the module substrate on which the plurality of memory devices are formed is supported by a supporter. The electronic system includes the semiconductor module.

Abstract: A solderable contact for use with an electrical component includes a pad metallization on a substrate, and an under bump metallization over at least part of the pad metallization. The under bump metallization is in an area for receiving solder. The pad metallization is structured to reveal parts of the substrate surface. The under bump metallization is in direct contact with the parts of the substrate.

Abstract: An integrated circuit package system includes: forming an external interconnect; forming a terminal having a cavity adjacent to and downset from a portion the external interconnect; connecting a first integrated circuit with the external interconnect; and forming an encapsulation over the first integrated circuit with cavity filled with the encapsulation, the terminal extending from the encapsulation, and the external interconnect partially exposed from the encapsulation.

Abstract: A wiring substrate includes plural wiring layers and plural insulation layers being alternately stacked one on top of the other. The plural insulation layers are formed with insulation resin having the same composition. The plural insulation layers are formed with a filler having the same composition. The filler content of each of the plural insulation layers ranges from 30 vol % or more to 65 vol % or less. The thermal expansion coefficient of each of the plural insulation layers ranges from 12 ppm/° C. or more to 35 ppm/° C. or less.

Abstract: A wiring process between the provided power semiconductor module and the external circuit is simple. In the power semiconductor module, a power semiconductor element and a cylindrical conductor are joined to one surface of a lead frame. An opening of the cylindrical conductor is exposed at a surface of transfer molding resin. Sealing with the transfer molding resin is performed such that terminal portions of the lead frame protrude from peripheral side portions of the transfer molding resin. The cylindrical conductor is conductive with a control circuit. The terminal portions of the lead frame are each conductive with a main circuit.

Abstract: The invention provides a semiconductor device including a rectangular chip provided on a mounting region of a substrate, a liquid resin layer provided under the rectangular chip and on a side surface of the chip, and a plurality of dams formed on the substrate so as to extend along the side surface of the rectangular chip. The configuration allows the semiconductor device to be provided with the substrate having a reduced size which is achieved by preventing a liquid resin from flowing out.

Abstract: A lead frame and an electronic package having improved adhesion between the lead frame and an encapsulating plastic material is disclosed. The lead frame can be pre plated having an outer layer comprising a precious metal such as palladium or gold to which is adhered a self-assembled monolayer (SAM), such as a SAM derived from an organophosphorus acid. The organophosphorus acid preferably is a mixture in which the organo groups are fluoro substituted hydrocarbons and hydrocarbons containing ethylenically unsaturated groups.

Abstract: A titanium-nickel-palladium solderable metal system for silicon power semiconductor devices (10), which may be used for one or both of the anode (20) or cathode (30). The metal system includes an outer layer of palladium (40,70), an intermediate layer of nickel (50,80), and an inner layer of titanium (60,90). For certain applications, the nickel may be alloyed with vanadium. The metal system may be deposited on bare silicon (100) or on one or more additional layers of metal (110) which may include aluminum, aluminum having approximately 1% silicon, or metal silicide. The use of palladium, rather than gold or silver, reduces cost, corrosion, and scratching.

Abstract: Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 ?m; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 ?m from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 ?m from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.

Abstract: A semiconductor device includes a conductive pattern formed on a substrate, a conductive land formed to come into contact with at least part of the top surface of the conductive pattern, and a conductive section formed on the conductive land. The conductive section is electrically connected through the conductive land to the conductive pattern.

Abstract: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit board with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.