Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: An apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device includes at least two main memory arrays comprised of a plurality of memory cells aligned in rows and/or columns and a shared redundancy circuit. The redundancy circuits preferably include a plurality of redundancy rows and a redundancy decoder which is configured for accessing the redundancy rows whenever a read or write operation involves use of a defective row within the main memory arrays for which a redundant row has been substituted. Preferably, each main memory array has access to the shared redundancy circuit. The shared redundancy circuit is used for substituting defective rows within a corresponding main memory array. The shared redundancy circuit provides extra redundant capacity to both of the main memory arrays.

Abstract: The cathode of the charging capacitor (31) of the present invention is coupled to a switch (36) that is able to apply one of several voltage levels to the cathode depending on the testing or use condition of the semiconductor memory array (10). The switch switches between the voltage levels at the cathode to avoid overstressing the charging capacitor (31) during testing of the semiconductor memory array (10).

Abstract: A data input/output circuit used to program the cells of a memory array or to determine the state of those cells. The circuit includes a data write path used for programming the memory cells in the array and a data read path for reading data indicative of the state of the cells. The data write path includes switching means for electrically disconnecting the high capacitance elements of the write path from the read path. The switching means is under the control of a control means which acts to enable or disable the switching means. The switching means serves to electrically isolate the high capacitance elements of the write path from the read path, thereby increasing the speed with which a read operation be performed.

Abstract: A field effect transistor (FET) is formed on a silicon on insulator (SOI) substrate in the thin silicon layer above the insulating buried oxide layer. A clock signal defines a clock period with an active portion and a wait portion. The source region and/or the drain region are coupled to a body pumping signal. The body pumping signal includes a negative voltage pulse occurring during the wait portion which sets the voltage of a body region of the FET to a preset voltage during such negative voltage pulse. Decay of the preset voltage is predictable such that operation of the FET can be controlled during the active portion.

Abstract: In a semiconductor memory device having redundant memory cells and sense amplifiers, when a redundant memory cell is accessed in place of a defective memory cell, the sense amplifier to which the defective memory cell is coupled and the redundant sense amplifier to which redundant memory cell is coupled are both activated simultaneously. Access to the defective memory cell is redirected to the redundant memory cell by switching data paths on a data bus to which both sense amplifiers are coupled. High-speed access is possible, because activation of the sense amplifiers and switching of the data paths take place concurrently.

Abstract: A semiconductor memory device with a write data masking method includes memory cell array divided into an even and an odd numbered memory cell array blocks for storing a first and a second data set, respectively, in response to even and odd numbered column selection signals, respectively. The device also includes an address generator for generating a column address in response to column addresses of multiple bits, an even and odd numbered column decoder for decoding the column addresses and generating the even and odd numbered column selection signals, respectively, in response to a first and a second masking control signal, respectively.

Abstract: Methods and systems consistent with the present invention store connection information in a memory of a node in a communications network such that the number of searches for retrieving the connection information is less than a predetermined probe threshold. The node includes a hash table and a connection table in the memory for storing and retrieving information associated with packets, frames, and/or cells in the communications network. Each entry in the hash table includes a connection identifier and, for example, a connection index, and is indexed according to a hash value based on the connection identifier. Each entry in the connection table includes connection state information that is indexed according to a connection index in the hash table. To store connection information in the memory, the node identifies in the hash table a first set of addresses that correspond to a first connection identifier.

Abstract: A circuit that prevents illegal transformation of data in a non-volatile memory comprises a three circuits which generate three reference currents of different amplitude, there comparison circuits which respectively compare the three reference currents with a cell current, a writing/deletion circuit which writes data in or deletes data from the cells. A control circuit is provided which outputs a corresponding information based on the result of comparison by the comparison circuit, and makes said writing/deletion circuit execute writing data in or deletion of data from a target cell once more when the cell current is greater than the second reference current or the cell current is not greater than the third reference current.

Abstract: A method for erasing a flash EEPROM device that includes a plurality of memory cells. The plurality of memory cells is erase verified and an erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle repeats until all cells verify as erased and a flag is set to NO. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached and the flag is set to YES. This cycle repeats until all cells verify as not being overerased. If it is determined after the overerase verification step that the flag is set to YES, the plurality of memory cells is again erase verified and the procedure repeats. If it is determined after the overerase verification step that the flag is set to NO, the erase procedure is considered finished.

Abstract: The objective of the invention is to read and write data in synchronization with a high-speed clock signal. The pulse width of the timing control signal (FY signal), which determines the pulse width of the column select signal (YS signal), is enlarged in a data read operation and reduced in a data write operation. In this way, the activation pulse width of the column select signal is enlarged in a data read operation and reduced in a data write operation. Consequently, in a data read operation, the time for connecting a bit line pair to an input/output line pair becomes longer. The potential difference of the bit line pair can be completely transferred to the input/output line pair. Therefore, data can be read correctly in synchronization with a high-speed clock signal.

Abstract: A non-volatile semiconductor memory IC has both a flash memory and a CPU mounted thereon. The CPU is provided with a ROM which stores a program code and a memory device such as a SRAM. The CPU functions by the stored program code to perform various functions such as accessing the flash memory to thereby carry out a test to determine a good/bad condition of the flash memory, temporarily storing results of the test in the memory device, and copying the test results from the memory device into the flash memory.

Abstract: A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data.

Abstract: A method and associated circuitry are disclosed for applying the high column segment voltages needed to erase and program (write) a segmented column flash EEPROM memory. Low voltage CMOS transistors are used for both the read column precharge path and the write/erase data transfer path. Also, the column segment select switch can be constructed of a single, low voltage, n-channel, transistor, rather than two complementary high voltage transistors. All of the above reduces precharge and discharge time, increasing the read speed of the memory. This also eliminates the lengthening of precharge time that occurs as the characteristics of high voltage transistors degrade with age. The present invention provides the additional advantage of eliminating the need to use less reliable high voltage transistors in certain off-pitch circuits needed for write and erase functions, thus increasing overall chip reliability.

Abstract: A current sensing amplifier for detecting a small current difference between a pair of variable resistance loads comprises a first amplifier and a second amplifier. The first amplifier comprises a voltage clamp including first and second outputs, the voltage clamp being coupled to the pair of variable resistance loads and substantially fixing a predetermined voltage across the variable resistance loads, the voltage clamp transferring the measured current difference to the first and second outputs. The first amplifier further includes a differential current source coupled to the first and second outputs. The second amplifier includes first and second inputs and an output, the first and second inputs being coupled to the first and second outputs, respectively, of the first amplifier.

Abstract: A memory device includes a memory array and at least two sets of row decoders to drive row lines in the memory array. Select lines (such as row select lines) carry signals to select one or more decoders in one of the two sets of decoders. At least some of the select lines are shared between the two sets of row decoders to decrease the space needed to route signal lines in the memory array.

Abstract: A low power, static content addressable memory having combinatorial logic gates to connect the selection lines of a plurality of memory cells in a manner that does not compromise the stability of the cells. In one embodiment, each memory cell has one set of complementary bit lines, while in a second embodiment, each memory cell has two or more sets of bit lines to allow simultaneous read operations or simultaneous read and write operations. Because precharging of the selection line is not required, the memory consumes less power in operation.

Abstract: A semiconductor memory includes: a plurality of memory cell transistors: a plurality of first bit lines; a plurality of second bit lines; a first transistor provided between a charging section for charging at least one of the plurality of first bit lines and the plurality of memory cell transistors; and a second transistor provided between a discharging section for discharging at least one of the plurality of second bit lines and the plurality of memory cell transistors, wherein one of a source region and a drain region of each of the plurality of memory cell transistors is formed as a part of one of the plurality of first bit lines, and the other of a source region and a drain region is formed as a part of one of the plurality of second bit lines; an ON/OFF state of the first transistor is controlled based on a first signal; an ON/OFF state of the second transistor is controlled based on a second signal; and the second signal is provided to the second transistor at a time which is delayed for a predetermined

Abstract: For cutting off a path for flowing a read detection current from a high-potential power supply (Vii) of a read data bus amplifier (S/B 33) to the ground side of a read controller (41) via a sense amplifier (31) selected based on an address in a write to a memory cell, a semiconductor memory device have a logic circuit (42, 43) for calculating logic between a block select signal and a write status signal to change the potential at the read controller (41) to the same power supply potential as that at the S/B (33) when the write status signal is activated. This logic circuit can prevent any unwanted read detection current from flowing in a data write, so as to suppress current consumption in a write.

Abstract: As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.