Abstract: An integrated circuit memory is capable of storing analog information without the need for A/D conversion. Samples of a analog signal input are stored in nonvolatile memory cells. The integrated circuit is also capable of storing digital information in digital form. The sampling rate at which the analog signal input is sampled is user selectable. An internal signal path of the integrated circuit memory is differential, which enhances the precision with which the analog signal is stored in the memory cells.

Abstract: The present invention relates to a sensing current reduction device for a semiconductor memory device, and a method therefor, which can considerably reduce a sensing current occupying a great part of an operating current and consume less power, by controlling a bit line sense amplifier to be operated after receiving a column address, and control a long-time operation not to be carried out after applying the row address. Accordingly, a time from latching a row address signal to receiving a column address signal is sharply decreased. As a result, an access time is reduced, thus achieving the high speed operation.

Abstract: A sense amplifier includes current mirror circuits, a NOR gate, inverters and a read data transition detection circuit. First and second read data respectively output from the inverters are input to the read data transition detection circuit. This read data transition detection circuit includes a NOR gate and outputs a logically low level transition detection signal to a data transition node when either of the first and second read data is at a logically high level. The output circuit corresponding to the sense amplifier receives the first read data in response to the transition detection signal. According to the constitution as described above, there can be provided a semiconductor memory in which the circuit scale is prevented from being unnecessarily enlarged and high speed access can be attained.

Abstract: The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.

Abstract: A complementary address generation circuit supplies a fuse select address signal as it is at a first fuse blow and converts the fuse select address signal to a complementary address and supplies the complementary address as an output at a second fuse blow. The output of the complementary address generation circuit is supplied to a fuse select circuit and the fuse select circuit selects a fuse group to which a substitution address is to be allocated. The fuse group used at the first fuse blow is selected in ascending order and at the second fuse blow the fuse group is selected in descending order. Thus, the spare used at the first fuse blow will be prevented from being used again in the second fuse blow and a repairable semiconductor memory device will not be rendered defective.

Abstract: A redundancy address in a plurality of memory devices is identified by at least two protocols available in an electric system. The first protocol is a mode register set command (or extended mode register set command). A chip select signal determines one of a plurality of memory modules, where a memory device is identified with at least one data port. Alternatively, a data strobe port or a data mask port may be preferably used for the selection of the memory devices instead of using the data port. The second protocol is a RAM access command which identifies a defective memory cell address (redundancy address) within the selected RAM by way of a plurality of address ports (ADRs). A redundancy address programming method is realized by way of electrically programmable fuses or by dynamically programmable redundancy latches integrated in each memory. The electric system configuration preferably includes a non-volatile storage device for storing a data port organization for the memory devices.

Abstract: Integrated circuit memory devices include one or more input receivers that have a reference voltage input terminal. A conductor electrically couples the reference voltage input terminals to a reference voltage, and a capacitor is connected between the conductor and a first ground voltage. Preferably, the location of the connection between the capacitor and the conductor is selected in accordance with the electrical characteristics of the input receivers. Accordingly, the capacitor may reduce fluctuations or noise in the reference voltage applied to the reference voltage input terminals of the input receivers. The fluctuations or noise in the reference voltage may cause the input characteristics and/or the set-up and hold times of the input receivers to vary with respect to one another. A reduction in fluctuations or noise in the reference voltage may result in more consistent input characteristics among the input receivers and more consistency in the set-up and hold times.

Abstract: A method is disclosed for alerting a user of a low power condition on, for instance, an FPGA interface device. An interface device having a microcontroller and an associated power plane for powering the microcontroller and other component on the interface device includes a detection circuit coupled to monitor the voltage level of the associated power plane. When the voltage level of the voltage plane falls below a predetermined threshold voltage, the detection circuit sends a low power flag to a host system. The low power flag, which is preferably sent to the host system using a USB port connection, alerts the host system of the low power condition on the interface device. The predetermined threshold voltage is selected to be a suitable amount higher than the minimum operating voltage for the microcontroller so as to allow sufficient time for the microcontroller to send the low power flag to the host system.

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract: In one embodiment of the present invention, a memory storage system for storing information organized in sectors within a nonvolatile memory bank is disclosed. The memory bank is defined by sector storage locations spanning across one or more rows of a nonvolatile memory device, each the sector including a user data portion and an overhead portion. The sectors being organized into blocks with each sector identified by a host provided logical block address (LBA). Each block is identified by a modified LBA derived from the host-provided LBA and said virtual PBA, said host-provided LBA being received by the storage device from the host for identifying a sector of information to be accessed, the actual PBA developed by said storage device for identifying a free location within said memory bank wherein said accessed sector is to be stored.

Abstract: The present invention disclosed the test cell and method of analyzing using the same which can analysis the cause of degradation of flash EEPROM cell in connection with programming, erasing or reading operation. The test cell comprises a first unit cell consisted of a drain, a source and a floating gate, a control gate; a second unit cell consisted of a drain, a source and a floating gate, control gate formed integrally with the floating gate and control gate of the first unit cell, respectively; and a third unit cell consisted of a drain, a source and a floating gate, a control gate formed integrally with the floating gate and control gate of the first unit cell, respectively.

Abstract: Apparatus and method of reading the state of each cell in a stacked memory comprising stacks of cells in an addressable array with each stack including MTJ memory cells stacked together with current terminals connected in series, and including a first and second current terminals coupled through an electronic switch to a current source. Each stack includes 2n levels of memory. A voltage drop across an addressed stack is sensed. Reference voltages equal to the 2n memory levels are provided and the sensed voltage drop is compared to the reference voltages to determine the memory level in the addressed stack. Encoding apparatus is used to convert the voltage drop to a digital output signal.

Abstract: In one embodiment, the present invention relates to a particular configuration of a non-volatile counter, which significantly reduces the amount of area required for implementation in an integrated circuit and improves its reliability of operation. This is accomplished by (1) replacing the volatile binary counter with a volatile counter coded for more equal distribution the changes in logic state over the entire counter, (2) replacing the non-volatile latch circuit with a single non-volatile memory element, and (3) developing testing techniques for complete and efficient testing of the critical non-volatile memory elements.

Abstract: A nonvolatile semiconductor memory device includes nonvolatile memory cells (C), constant voltage circuits for applying one of different verify voltages to control gates of the nonvolatile memory cells C in response to control data introduced into the memory device from the exterior, and writing and sensing circuit circuits for applying a potential to drains of the nonvolatile memory cells C in response to write data introduced into the memory device and for detecting and amplifying currents between drains and sources of the nonvolatile memory cells. By dividing the memory cell array 501 and a serial register 502 into some parts and by connecting an external SRAM 503 so as to progress the transfer of data from the memory cell array 501 to the serial register 502 and the transfer of data from the serial register 502 to the external SRAM 503 in parallel, the read speed is increased.

Abstract: A semiconductor device is equipped with an improved programmable impedance output buffer driver which makes it possible to adjust the impedance of the output buffer of the semiconductor device to the impedance of the bus lines of the system bus in a normal operation mode and to adjust the impedance of the output buffer of the semiconductor device to a predetermined fixed impedance in a test mode. It is therefore possible to effectively and accurately conduct tests of the semiconductor device.

Abstract: The present invention enables efficient start-up of integrated circuit at low voltages. The present invention disconnects the output load from the circuit by placing the circuit connected to the output load into a high impedance state. Thus, the internal voltage of the circuit can be boosted before it is subject to drain from an external load. A comparator is connected to the circuit placed in the high impedance state and determines when the internal voltage has reached a sufficient level so that the effect of the external load on the efficient operation of the circuit will be minimized.

Abstract: In a DRAM with an antifuse for programming a defective address, the antifuse and one electrode of a capacitor are connected to a shared node and the other electrode of the capacitor receives a boost signal. To blow the antifuse, the shared node is set high. To maintain the antifuse unblown, the shared node is set low. Then the boost signal is raised high to boost the shared node. Even when the resistance value of antifuse 1 is decreased, excessive current does not flow. This eliminates the necessity of providing a protection circuit as conventional and thus reduces circuit scale.

Abstract: A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5> and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.

Abstract: A dynamic random access memory circuit achieves much higher data bandwidth by maximizing the number of memory cell rows that are held open and by indefinitely increasing the time that the rows are open. The boosted voltage of a pump circuit is directed to active rows according to the presence of a pump token. The pump token is present at one location in a circular shift register corresponding to a memory array. The concurrence of the token and a pump-enable signal causes that array to receive a boosted voltage independent of an array-select operation.

Abstract: A keeper circuit (14) is included in a memory arrangement comprising a column of memory cells (20) connected by a bit line pair (16,18). The keeper circuit (14) comprises two keeper transistors. One keeper transistor (86) is connected to control current from a supply voltage source to one bit line (16) and the other keeper transistor (88) is connected to control current from the supply voltage source to the other bit line (18) of the bit line pair. Current through each keeper transistor (86, 88) is controlled by the charge state of the opposite bit line. A low charge state on one bit line causes the keeper transistor associated with the opposite bit line to conduct and maintain the charge level of the opposite bit line.