Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A ternary content addressable memory (CAM) cell. For one embodiment, the ternary CAM cell includes a first memory cell, a compare circuit, a second memory cell and a mask circuit. The first memory cell is coupled to a first pair of bit lines that carries data to and from the first memory cell. The compare circuit receives comparand data on a pair of compare signal lines, and compares the comparand data with the data stored in the first memory cell. The compare circuit includes a pair of transistors and a match transistor. The pair of transistors receives the comparand data on the compare signal lines and also receives the data stored in the first memory cell. The match transistor determines the state of a match line. The second memory cell stores mask data that may mask the comparison result such that it does not affect the logical state of the match line.

Abstract: A RAMBUS dynamic random access memory includes a test control circuit that selectively couples a row address latch to either a row sense control signal or a CMD control signal. In a normal operating mode, the test control circuit couples the row address latch to the row sense control signal so that the row sense control signal both latches a row address and senses a row of memory cells corresponding to the latched address. Prior to conducting a core noise test, the test control circuit couples the row address latch to the CMD control signal so that the row address is latched by the CMD control signal, and the row sense control signal only functions during the core noise test to sense a row corresponding to the latched row. The memory also includes a multiplexer that receives a time-multiplexed data/address bus and simultaneously couples a first part of the data/address bus to an internal data bus and a second part of the data/address bus to an internal address bus.

Abstract: Clock generating circuits include a clock buffer, a delay mirror circuit (DMC), a clock frequency divider circuit and a clock generator circuit. The clock buffer is responsive to an external clock signal EXTCLK and generates a buffered clock signal ICLK in response to the external clock signal EXTCLK. The buffered clock signal ICLK is delayed relative to the external clock signal EXTCLK by a fixed buffer delay time "dtb". The delay mirror circuit (DMC) is responsive to the buffered clock signal ICLK and generates a delayed clock signal IDCLK. The delayed clock signal IDCLK is delayed relative to the buffered clock signal ICLK by a fixed delay-mirror time "dtot". The clock frequency divider circuit is responsive to the buffered clock signal ICLK and the delayed clock signal IDCLK. The clock frequency divider circuit includes first and second divider devices that generate first and second divided clock signals VDIV1 and VDIV2, respectively.

Abstract: A flash memory cell. The flash memory cell includes first and second transistors. The first transistor has a control gate coupled to a word line, a drain coupled to a data line and a floating gate. The second transistor, similarly, includes a control gate coupled to the word line, a drain coupled to a second data line and a second floating gate. The first floating gate stores a state of the second transistor prior to programming of the flash memory cell. Further, the second floating gate stores a programmed state of the second transistor. A difference between the states of the first and second transistors represents the value of the data stored in the flash memory cell.

Abstract: A semiconductor memory device including at least three of the following cell structures: an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure. The cell structures are disposed on the same substrate and preferably have gate surfaces which are substantially coplanar. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, FERAM, DRAM, and/or SRAM memory structures on one substrate and processes for forming a new NVRAM cell structure.

Abstract: A multi-chip sensing device package and a method for forming such package are disclosed. The multi-chip sensing device package is built on an electrically insulative substrate such as a ceramic material, by using a thick film printing technique to print a multiplicity of bonding pads including interconnection pads and output pads on the surface of the rigid, insulated substrate. After a plurality of sensing elements are bonded by solder to the plurality of bonding pads, the sensing device may be connected to either lead fingers of a lead frame, or to J-leads formed integral with the device for providing electrical communication with an external circuit. The device may further be packaged in a plastic housing with a top surface of the device exposing to the environment for performing its detection function.

Abstract: A Rambus in-line memory module may be adapted for the smaller board size used for example with portable computers. By using wrong-way routing, the routing can be achieved in a small size while matching impedance between the routings. By grouping signals on one side of the module's printed circuit board and ground and power supplies contacts on another side of the board, performance may be improved.

Abstract: A method for programming an electrically erasable programmable read only memory (EEPROM) while mounted on a printed circuit board. The EEPROM is used as a memory storage device for a field programmable gate array (FPGA), which is mounted on the printed circuit board. The board and FPGA have a joint test action group (JTAG) test interface. The FPGA contains a test access port (TAP) and user defined internal scan registers. The method includes providing a connection between the TAP of the FPGA and the EEPROM. Data is provided to the internal scan data registers of the FPGA via the JTAG test interface. Data is transferred via the internal scan data registers to the EEPROM without interrupting operation of the FPGA.

Abstract: A memory cell array includes a plurality of memory cells connected in series, and each of the memory cells is constituted of an EEPROM. A bit line is connected to one end of the memory cell array, and a source line is connected to the other end thereof. A source line bias circuit is connected to the source line. The source line bias circuit supplies a voltage, which is higher than a power supply voltage and lower than an erase voltage in a data write mode, to the source line to precharge the voltage of channels of the memory cells higher than the power supply voltage. After that, a voltage is applied to the control gates of the memory cells to boost the precharged voltage further by capacitance coupling of the channels and control gates. It is thus possible to prevent data from being erroneously written to a memory cell for writing "1" data.

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Abstract: An analog read circuit includes an output transistor connected to a memory cell to be read, and an operational amplifier having a non-inverting input connected to the drain terminal of the memory cell, an inverting input connected to a reference terminal, and an output, forming the output of the reading circuit and connected to the gate terminal of the output transistor. Bias transistors maintain the memory cell and the output transistor in the linear region, and the operational amplifier and the output transistor form a negative feedback loop so that the output voltage V.sub.O of the read circuit is linerly dependent upon the threshold voltage the memory cell. The reading circuit has high precision and high reading speed.

Abstract: A built-in flash memory and an ATA controller portion are integrated onto one chip, and a controller connection interface is also provided. Semiconductor devices can be interconnected by the controller connection interface. The semiconductor device senses the input conditions of control signals and a data bus according to timing at which a reset signal is cancelled immediately after power on, and determines if it is operates as an ATA controller or an expanded flash memory.

Abstract: A method and apparatus controls the memory access of memory devices in order to utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.

Abstract: A non-volatile semiconductor memory device is provided with a circuit that protects a tunnel oxide film from the charging phenomenon. This circuit comprises a first junction diode including an N.sup.+ -type diffusion layer and a P-type well, and a second junction diode including a P-type well and an N-type well. When a voltage applied to the control gate is greater than all of a write voltage, a read voltage, and an erasure voltage that would be applied to the control gate, a current is guided through that circuit.

Abstract: Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals are dependent upon the levels of programming reference signals used for controlling the programming of the memory cell. The memory cell can thus be programmed without reading out its memory state during the programming process, with programming margins being assured by the dependence of the read reference signals on the programming reference signals. Both sets of reference signals may be generated by reference cells which track variations in the operating characteristics of the memory cell with changes in conditions, such as temperature and system voltages, to enhance the reliability of memory programming and readout.

Abstract: It includes: a substrate; a plurality of optical data processing units arranged in an array on the substrate, a super graphite sheet on LEDs of the optical processing units, and a glass substrate on the super graphite sheet. Each optical data processing unit includes an optical signal receiving circuit on the substrate for receiving an optical signal and generating a reception signal; a data processing circuit on the substrate for processing the reception signal and generating resultant data; a drive circuit and an LED on the substrate for emitting an output optical signal and heat in accordance with the resultant data. The super graphite sheet on the LED transmits and radiates the heat from the LEDs. The super graphite film is provided by sintering a high polymer sheet and has a high heat conductivity.

Abstract: A device for directly loading data onto bit lines of DRAMs. The device eliminates the need for performing a read cycle prior to a write cycle by bypassing the sense amplifiers of the DRAM. An I/O data line is connected to a bit line by a first transmission gate. A second transmission gate is electrically connected between the first transmission gate and the sense amplifier. A voltage level representing a data bit is loaded directly onto a bit line by turning off the second transmission gate to isolate the sense amplifier from the bit line and turning on the first transmission gate to connect the data line to the bit line. The voltage level on the bit line is then stored in a memory cell connected to the bit line.

Abstract: A ferroelectric memory cell integrated with silicon circuitry which require a forming-gas anneal of the silicon circuitry after the ferroelectric stack has been formed. The ferroelectric layer may have a composition such that there is no space in the lattice of the ferroelectric phase to accommodate atomic hydrogen or have a composition with a Curie temperature below the temperature of the forming-gas anneal. Preferably, there is no upper platinum electrode, or it is deposited after the forming-gas anneal. A metal-oxide upper electrode serves as barrier to the forming-gas anneal, and an intermetallic layer positioned above the ferroelectric stack serves as an even better barrier. Forming-gas damage to the ferroelectric stack can be removed by a recovery anneal in a hydrogen-free environment, preferably performed at a temperature above the Curie temperature.

Abstract: The present invention relates to a memory device including memory cells each formed of a cell transistor connected to bit and word line and a cell capacitor. The memory device includes a pre-charging circuit for pre-charging bit line to a first voltage, a sense amplifier for detecting voltages of bit lines and driving the bit lines to a second voltage for H level or a third voltage for L level, and a word line driving circuit for driving word lines to make the writing voltage for H level of the cell capacitor to a fourth voltage lower than the second voltage. The present invention is characterized in that the first voltage is lower than an intermediate value between the second and third voltages. According to the present invention, it becomes possible to prevent the voltage V.sub.