Patents Examined by Terrence Willoughby
  • Patent number: 8120883
    Abstract: The present invention is directed to an electrical wiring protection device that includes a housing assembly having a plurality of line terminals and a plurality of load terminals. A fault detection circuit is coupled to at least one of the plurality of line terminals and configured to generate a fault detection signal in response to detecting at least one fault condition in the electrical distribution system. A circuit interrupter assembly is coupled to the fault detection circuit. The circuit interrupter assembly is configured to couple the plurality of line terminals to the plurality of load terminals to form a conductive electrical path in a reset state, and decouple the plurality of line terminals from the plurality of load terminals in response to a fault detection signal in a tripped state.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: February 21, 2012
    Assignee: Pass & Seymour, Inc.
    Inventors: Kent R. Morgan, Richard Weeks, Gerald R. Savicki, Jr., Kenneth D. Vought
  • Patent number: 8116058
    Abstract: The present invention contemplates systems and methods for distributing RF and DC signals and detecting, logging and suppressing surge energy associated with surge events such as lightning and power line surges. The detection and logging is provided in order to determine possible causes of a failure and who might be responsible for the repair. The suppression is provided in order to protect electrical equipment such as split mount wireless radio systems from catastrophic failure due to surge events.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: February 14, 2012
    Assignee: Harris Stratex Networks Operating Corporation
    Inventors: Youming Qin, Frank S. Matsumoto, David C. M. Pham
  • Patent number: 8102634
    Abstract: A differential protection method in a power network for determining type of fault occurring within the power network. The power network includes a protected object having two or more ends, and a current differential protection device and a current transformer are arranged at each end. The method includes the steps obtaining, at a first end of the protected object, measured values from a second end of the protected object; comparing, at the first end, changes in measured values taken at the first end with changes in the measured values obtained from the second end; and determining, upon the step of comparing changes in measured values showing differing results, type of fault occurring within the power network.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: January 24, 2012
    Assignee: ABB Technology AG
    Inventors: Zoran Gajic, Bertil Lundqvist
  • Patent number: 8089744
    Abstract: An integrated circuit (IC) includes a multiple-finger transistor structure. The multiple-finger transistor structure includes one transistor configured as a ballasted device. The multiple-finger transistor structure further includes a second transistor configured as a trigger device for the ballasted device.
    Type: Grant
    Filed: August 24, 2005
    Date of Patent: January 3, 2012
    Assignee: Altera Corporation
    Inventors: Irfan Rahim, Cheng Hsiung Huang, Yow-Juang Bill Liu, Jeffrey T. Watt, Hugh Sung-Ki O
  • Patent number: 8072721
    Abstract: An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: December 6, 2011
    Assignee: Hong Kong Applied Science and Technology Research Institute Co., Ltd.
    Inventors: Kwok Kuen David Kwong, Chik Wai David Ng, Wai Kit Victor So, Hing Kit Kwan
  • Patent number: 8059380
    Abstract: A semiconductor package includes an electrostatic discharge rail capable of being coupled to a first conductive contact and a second conductive contact, a first portion of a voltage triggerable material between the electrostatic discharge rail and the first conductive contact; and a second portion of the voltage triggerable material between the electrostatic discharge rail and the second conductive contact. The first and second conductive contacts may be coupled to the same semiconductor device or different semiconductor devices.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: November 15, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sergio A. Ajuria, Melanie Etherton, Marc A. Mangrum
  • Patent number: 8050008
    Abstract: A relay device includes mechanical relays, a first bus bar, a second bus bar, and a relay drive circuit. The relay includes a coil, a moving contact whose position changes according to whether the coil is energized, a load terminal conductive to the contact and connected to the first bar, and a coil terminal connected to the coil and second bar. The first bar includes a loading circuit. A current flows to an external load through the loading circuit opened/closed when the position of the contact changes. The second bar includes a coil circuit through which the coil is energized. The drive circuit is packaged on the second bar and opens/closes the coil circuit based on an operation signal. The first and second bars are stacked at predetermined intervals. The relays are between the first and second bars.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: November 1, 2011
    Assignee: Anden Co., Ltd.
    Inventor: Hirohisa Suzuki
  • Patent number: 8045312
    Abstract: In one embodiment, there is provided a printed circuit board including a first rigid circuit board layer having a first signal trace arrayed on it, a second rigid circuit board layer having a second signal trace arrayed on it, a first signal path coupled between the first signal trace and the second signal trace, an electrostatic discharge device located between the first rigid circuit board layer and the second rigid circuit board layer, the electrostatic discharge device having a first electrode coupled to the first signal path, an electrostatic discharge reactance layer coupled to the first electrode, and a second electrode coupled to the electrostatic discharge layer but not coupled to the first signal path. The circuit board also having a ground plane, where the ground plane is coupled to the second electrode.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: October 25, 2011
    Assignee: Electronic Polymers, Inc.
    Inventor: Karen P. Shrier
  • Patent number: 8031451
    Abstract: A solid state power control module contains non-volatile memory. A switch for opening is provided to break a supply of power to a component. The switch is operable to trip (open) when an undesirable condition is detected, and further to be opened upon receiving a control signal. A status of the switch is stored in the non-volatile memory. A detector is provided for identifying when a module has been mounted in a housing, and communicates with the non-volatile memory if it is determined that the module is newly installed in a housing. A system and method are also claimed.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: October 4, 2011
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Bruce D. Beneditz, Jeffrey T. Wavering, Dennis R. Anderson, Josef Maier, Mark Hamilton Severson, Massoud Vaziri
  • Patent number: 8027133
    Abstract: A power plate for driving a robot is provided herein. The power plate is capable of driving the robot in a stable manner. This stable drive of the robot is achieved by preventing a whole system paralysis phenomenon, which is caused by a local short-circuit occurring in a certain part of the power plate. The whole system paralysis is prevented by selectively breaking power supplied to a power supply pattern in association with the part where the short-circuit occurs.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: September 27, 2011
    Assignee: IR Robot Co. Ltd.
    Inventor: Chang Hyun Park
  • Patent number: 7268992
    Abstract: A power supply in which a feed voltage (Us) is guided through at least one longitudinal branch to at least one output, the at least one branch having a disconnect fuse formed as a controlled semiconductor switch (SW1) and a monitoring unit (UWE) being set up to supply a disconnect signal (s1) to the semiconductor switch when there are changes in voltage or current beyond pre-definable tolerances, in which at least one auxiliary semiconductor switch (H1A), likewise triggered by the monitoring unit (UWE), is connected in parallel to the semiconductor switch (SW1) and in the event of an overload absorbs a substantial portion of the overload current in the branch.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: September 11, 2007
    Assignee: Siemens AG Österreich
    Inventors: Jalal Hallak, Harald Schweigert
  • Patent number: 7268990
    Abstract: A power amplifier protection circuit that includes protection circuitry to variably shunt an input radio frequency (RF) signal to AC ground, turn off bias to an output transistor of a power amplifier, and turn off the output transistor. The power amplifier protection circuit features an asymmetrical control that can quickly shut off a power amplifier, and turn on the power amplifier at a steady, controlled rate when an output transistor exceeds a predetermined threshold voltage.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: September 11, 2007
    Assignee: Marvell International Ltd.
    Inventors: Wayne Loeb, Alireza Shrivani-Mahdavi
  • Patent number: 7264081
    Abstract: In a hearing protection earplug for insertion into the ear canal ear composed of a soft material, especially a foam material, having a cavity that is open toward the outside, it is provided, with a view to achieving additionally increased wearing comfort accompanied with easy handling during insertion into and removal from the ear, that the cavity, as seen in the cross-section, has an approximately cross-shaped configuration.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: September 4, 2007
    Assignee: Uvex Arbeitsschutz GmbH
    Inventor: Stefan Bruck
  • Patent number: 7259951
    Abstract: A semiconductor device comprises an output transistor for controlling current that flows between a first terminal and a second terminal, a detection transistor connected in parallel with the output transistor, a detection resistor connected in series with the detection transistor, for detecting current that flows through the detection transistor as detection voltage and of which the resistance value is set in proportion to the potential difference between the first terminal and the second terminal and an over-current protection transistor for decreasing the ON current of the output transistor and the detection transistor according to the increase of the detection voltage.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: August 21, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Takao Arai
  • Patent number: 7245474
    Abstract: A circuit arrangement and also a method for controlling a bistable magnetic valve in which a magnetic valve is to be supplied with a pulse of electrical current in order to switch over the magnetic valve from a first stable state into a second stable state, comprises a power supply source to provide a supply voltage, a power supply device fed by the power supply source and able to be activated for the duration of the current pulse by an entered control signal (Enable) to create a coil current (I) flowing through the magnetic coil, with the coil current (I) being set to a setpoint, where changeover means are provided in order to reduce the setpoint of the coil current during the current pulse. This advantageously allows the power dissipation of the activation of bistable magnetic valves to be reduced.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: July 17, 2007
    Assignee: Siemens Aktiengesellschaft
    Inventors: Stephan Bolz, Günter Lugert
  • Patent number: 7236344
    Abstract: The apparatus for generating ionic flow of media includes a DC voltage supply having a positive terminal and a negative terminal with a collector connected to the negative terminal of the direct current voltage supply. The collector has a substantially tubular configuration with a rear and front section with inwardly tapering frusto-conical section therebetween. An emitter pin is connected to the positive terminal of the direct current voltage supply with the majority of the tip being located within the frusto-conical section of the collector. Alternatively, the front section of the collector may be made of a dielectric material, such as plastic. As a result, fluid flow, such as air flow, is generated from the input port of the rear section of the collector, through the frusto-conical section of the collector and out the output port of the front section of the collector.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: June 26, 2007
    Assignee: Cool Shield, Inc.
    Inventor: Kevin A. McCullough
  • Patent number: 7233475
    Abstract: MOS Transistors and bipolar junction transistors are connected to input pads and output pads for implementing electrostatic discharge protection. By conducting a power clamp circuit and applying a substrate-trigger technology, electrostatic discharge protection is further enhanced. For instance, positive ESD stress protection can be enhanced between signal pads (input pads and output pads) and VSS by using NMOS transistors and field oxide devices. Negative ESD stress protection can be enhanced between signal pads and VDD by using PMOS transistors.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: June 19, 2007
    Assignee: Novatek Microelectronics Corp.
    Inventor: Shiao-Shien Chen
  • Patent number: 7233470
    Abstract: A distance relay apparatus includes a directional relay element which performs computation to detect a fault, which occurs in the forward direction from an installing point of the relay apparatus, based on a voltage and a current which are received from an object to be protected, a zone-1 distance relay element which performs computation to detect a fault within a predetermined zone, a fault detecting relay element which performs computation to detect a fault within a zone that is narrower than that of the zone-1 distance relay element in terms of data time length which is shorter than that used for the computation of the zone-1 distance relay element, and a logic element which outputs a relay signal in accordance with a detecting operation of the zone-1 distance relay element, the fault detecting relay element, and the directional relay element.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: June 19, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takahiro Kase, Hidenari Amo, Tetsuo Matsushima
  • Patent number: 7233462
    Abstract: An overcurrent protection circuit for a voltage regulator has a first transistor having a gate for connection to a gate of an output transistor of the voltage regulator, a resistor connected to a drain of the first transistor, an output voltage detecting transistor having a gate connected to an output terminal of a dividing resistance circuit of the voltage regulator, and a current mirror circuit having an input terminal connected to the drain of the output voltage detecting transistor. A second transistor has a gate connected to the drain of the first transistor and a drain connected to an output terminal of the current mirror circuit. A third transistor has a gate connected to the output terminal of the current mirror circuit and a drain for connection to the gate of the output transistor of the voltage regulator.
    Type: Grant
    Filed: November 3, 2005
    Date of Patent: June 19, 2007
    Assignee: Seiko Instruments Inc.
    Inventor: Yoshihide Kanakubo
  • Patent number: 7223922
    Abstract: A cable having an electrostatic discharge (ESD) dissipative coating. The cable includes a lead and an ESD dissipative coating operatively coupled to the lead. Other layers such as adhesives and insulating layers can be provided. The ESD dissipative coating can also function as the insulator for the lead.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: May 29, 2007
    Assignee: International Business Machines Corporation
    Inventors: William Thomas Bandy, IV, Icko Eric Timothy Iben, Peter John Golcher, John Bradley Kriehn, Ho-Yiu Lam, Jeffrey Serrell Snyder, Larry LeeRoy Tretter, George G. Zamora