Patents Examined by Terrence Willoughby
  • Patent number: 7218496
    Abstract: The voltage generator circuit includes a regulator, a first sensor circuit, and a second sensor circuit. The first sensor circuit includes a first transistor, a first resistor, and an error amplifier. When V1>Vth, the error amplifier senses an overcurrent condition to provide feedback to the operational amplifier to limit an output current. The second sensor circuit includes a second transistor, a second resistor, and a sensing transistor. When the output current exceeds a sense threshold current, the sensing transistor is turned ON to provide feedback to the operational amplifier 12 to limit the output current. The second sensor circuit has a higher setting of sense threshold current than does the first sensor circuit, while having a higher setting of sensing speed than does the first sensor circuit.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: May 15, 2007
    Assignee: Rohm Co., Ltd.
    Inventor: Atsushi Kitagawa
  • Patent number: 7218492
    Abstract: A device (10) for suppressing electrostatic discharge comprises first and second multilayer structures (14, 16) surrounding an electrostatic discharge reactance layer (12), the resistance of said electrostatic discharge reactance layer (12) varying in response to the occurrence of an electrostatic discharge signal. Each multilayer structure (14, 16) comprises a barrier layer (18), a terminal layer (20) and an electrode layer (28). Alternatively, a conductive layer (80) can be used instead of a second multilayer structure (16). An ESD suppression device (110) can be embedded in a printed circuit board (122, 210) providing a way to protect board components from harmful ESD events.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: May 15, 2007
    Assignee: Electronic Polymers, Inc.
    Inventor: Karen Pamelia Shrier
  • Patent number: 7212387
    Abstract: ESD protection circuitry for a signal power supply pad (801) comprising a discharge circuit (802) operable to discharge the ESD pulse to ground, and a precharge reduction circuit (810) in parallel with the discharge circuit. This precharge reduction circuit is operable to cancel any precharge voltage to ground before an ESD event, and also to discharge any trailing pulse to ground after an ESD event. The reduction circuit comprises a discharge resistor (811), preferably about 10 k?, connected to the discharge circuit, and a control MOS transistor (812) in series with the discharge resistor. The transistor source (812a) is connected to the resistor, the drain (812b) to ground, and the gate (812c) to core power (813) so that the transistor is shut off during IC operation and conducting when pre-charge or post-charge is present at an ESD pulse.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: May 1, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Charvaka Duvvury, Chih-Ming Hung
  • Patent number: 7206182
    Abstract: A negative ions generating circuit design with decreasing high frequency noise includes a power indication circuit, an oscillation circuit, an amplifying circuit and a radial frequency filtering circuit. The power indicating circuit, the oscillation circuit and the amplifying circuit are used for generating negative ions. The radial frequency filtering circuit has a capacitance to be utilized for limiting the high frequency in a coil so that the high frequency will not be amplified by through the transistor of the oscillation circuit. The coil creates an inductance to limit the high frequency so as to effectively eliminate the high frequency created by the oscillation circuit.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: April 17, 2007
    Inventor: Hsin-mao Hsieh
  • Patent number: 7199989
    Abstract: In a digital protection relay with a time sync function, the sampling timing of which is specified based on a reference timing transmitted from a time signal generator to a time sync unit, with a determination value. The time sync unit includes a reception circuit that receives a discrimination code and time data transmitted from the time signal generator, a code discrimination circuit that discriminates the reference timing on condition that the received discrimination code coincides with a desired code, a time calculation circuit that calculates the sampling timing on the basis of the discriminated reference timing and the time data, and a sampling sync circuit that specifies the sampling timing of a digital quantity of electricity on the basis of the calculated sampling timing.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: April 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daiju Itagaki, Hiroaki Ayakawa, Itsuo Shuto
  • Patent number: 7196894
    Abstract: The method according to the invention for demagnetization is effected in two separate steps. Firstly magnetically hard locations, such as weld seams, pressure locations etc., of an object to be demagnetized is pre-treated locally with high fields by way of choke coils in an alternating field. These magnetically hard locations are at least partly demagnetized by way of this. Subsequently the complete demagnetization is effected in a decisive second step. The object remains for a certain time in an alternating field. Now the alternating field is stepped down in that the current in a series oscillation circuit is stepped down in a current-controlled manner with two coils.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: March 27, 2007
    Inventors: Albert Maurer, Urs Meyer
  • Patent number: 7196884
    Abstract: Disclosed is an apparatus and method for detecting a loss of a current transformer connection coupling a protective relay to a power system element of a three-phase power system and providing a plurality of secondary current waveforms of the three-phase power system to the protective relay. The apparatus includes a first logic circuit and a second logic configured to provide corresponding first and second binary signals in response to respective comparisons of calculated current value(s) of a plurality of like-phase digitized current sample streams to respective threshold values. The apparatus also includes a set reset flip-flop having a set input adapted to receive the first and second binary signals to provide a third binary signal. The third binary signal indicates loss of a current transformer connection when the set input is asserted and indicates no loss of a current transformer connection when the reset input is asserted.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: March 27, 2007
    Assignee: Schweitzer Engineering Laboratories, Inc.
    Inventors: Armando Guzman-Casillas, Normann Fischer
  • Patent number: 7170729
    Abstract: A semiconductor integrated circuit of the present invention includes, between a power line 1 and a ground line 2, an NMIS transistor 3 capable of supplying fixed signals with low and high levels to the outside, an NMIS transistor 6 having a source connected to a gate of the NMIS transistor 3, a PMIS transistor 7 having a drain connected to a gate of the NMIS transistor 6, and an ESD protection power clamp circuit 14. If a surge is applied to the power line 1, the ESD protection power clamp circuit 14 is clamped to pass the surge to the ground line. While the surge is passed, the potential of the power line 1 rises to turn on the three transistors 3, 6, and 7. At this time, the NMIS transistor 6 and the PMIS transistor 7 can reduce the gate potential of the NMIS transistor 3 lower than the potential of the power line 1.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: January 30, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroaki Yabu
  • Patent number: 7161786
    Abstract: A data surge protection module which can be added to data and control networks not having such protection. The use of quick connect/disconnect connectors allows the rapid installation or replacement of such modules. a built in ground plate and a braided low impedance conductor offer alternative grounding methods for the module. The module employs two or more diode steering bridges and uses a diode as the surge suppression element.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: January 9, 2007
    Assignee: Leviton Manufacturing Co., Inc.
    Inventors: Robert Bencivenga, Matthew Wakeham, Yoshiharu Sueoka, Pieter Loftus
  • Patent number: 7161783
    Abstract: In an overcurrent protection circuit for a switching power supply having multiple voltage supply sections, an overcurrent in a low voltage supply section is detected to make it possible to take a countermeasure against overload in a transformer winding, using a simple and low cost circuit design. The circuit comprises: a current detection resistor 33 to detect a current in secondary side of the transformer; transistors 53 and 52 to be turned on by the current detection; a photocoupler 50 to be turned on and off by the transistors; and a switching power supply controller 7 to control on-duty of a power MOSFET 6 for removing the overcurrent. The current detection resistor 33 is provided in the line of a secondary winding 30 so as to be able to individually limit a current flowing through the secondary winding 30.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: January 9, 2007
    Assignee: Funai Electric Co., Ltd.
    Inventor: Katsuyuki Yoshida
  • Patent number: 7158360
    Abstract: A solenoid drive circuit includes a control circuit which comprises a detector with a resistor for discerning current flow therethrough to produce electric signals that correspond to level of current flow through a solenoid connected to the resistor; an amplifier for amplifying the electric signals from the resistor; and an integrator for integrating the amplified output from the amplifier.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: January 2, 2007
    Assignee: Sanken Electric Co., Ltd.
    Inventors: Kiyokatsu Satoh, Masaki Kanazawa
  • Patent number: 7154728
    Abstract: The active part which is provided for use in a surge arrester includes two connecting fittings, which are arranged along an axis at a distance from one another, at least one cylindrical varistor column, which is provided between the two connecting fittings, and at least one dielectric loop. This loop is supported on the two connecting fittings and thus holds the active part together, thus forming a contact force. The active part is distinguished by a small physical height and little use of materials. This is achieved in that at least one of the two connecting fittings has an electrode, which is arranged at right angles to the axis and is in the form of a plate, as well as an electrical connection, which is integrally formed on the plate. Furthermore, supporting means which are in the form of shoulders are provided for the dielectric loop, and are formed in the plate and/or are integrally formed at the edge of the plate.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: December 26, 2006
    Assignee: ABB Technology AG
    Inventors: Walter Schmidt, Robert Hauser
  • Patent number: 7154726
    Abstract: The pluggable electrical apparatus, formed in particular as a surge arrester (A), has an axially symmetrical housing (1) with a housing axis (7) running in the plugging direction, a flange (5) for fastening the apparatus housing (1) on a housing (30) of a high-voltage installation (H) and an axially symmetrical active part (6). In order to make it possible for this apparatus (A) to be fitted into the high-voltage installation (H) in a simple manner, the flange (5) is formed into the apparatus housing (1) and the active part (6) is mounted displaceably in the axial direction in the apparatus housing (1) and held with a prestressing force with respect to the apparatus housing (1) before a plug-in connection is formed.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: December 26, 2006
    Assignee: ABB Schweiz AG
    Inventors: Jutta Barlage, Peter Zeller, Sarah Sitzler
  • Patent number: 7151655
    Abstract: An electrostatic discharge (ESD) detector and a system having an ESD detector have been described herein.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: December 19, 2006
    Assignee: Intel Corporation
    Inventor: Wei Chien Choo
  • Patent number: 7149063
    Abstract: An electrical connector and methods for minimizing arcing when the connector is connected or disconnected under load are disclosed. The invention provides an arc reduction circuit with one or more regulators, such as transistors, integrated into the connector housing that sense movement of the connector and shunt the current to an impedance circuit when a potential arc condition is sensed.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: December 12, 2006
    Assignee: Tyco Electronics Corporation
    Inventors: Lyle S. Bryan, Jeremy C. Patterson, Edwin G. Cox
  • Patent number: 7139157
    Abstract: A field effect transistor (FET) is used as the protection circuit. The gate is grounded through an electrical element. The voltage source is connected to the drain of the FET. The load is connected to the source of the FET. At low input voltages, the FET conducts in body diode mode. At higher input voltages, the FET turns “on” and conducts more efficiently.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: November 21, 2006
    Assignee: Kyocera Wireless Corp.
    Inventor: John P. Taylor
  • Patent number: 7133272
    Abstract: A solid-state direct replacement relay assembly, and a method for installing and using it to replace the mechanical-style relays in the electrical cabinets of a locomotive. Solid-state relay components are substituted to upgrade locomotive relay systems, and to improve train controls. Normally solid-state relays cannot directly handle standard locomotive voltages without an external power supply that requires modification to the original train design and wiring. The solid-state relay assembly is coupled to a D.C./D.C. converter, which steps 75 volts down to approximately 5–32 volts, and is used to control the solid-state relay assembly. The use of the solid-state relay assembly device requires no modification to the existing electrical wiring system of any new or old locomotive.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: November 7, 2006
    Inventors: Steve R. Stanick, Michael A. Meyers
  • Patent number: 7133270
    Abstract: An electrical power breaker includes an electronic protective device and an electronic memory. The memory is accommodated in the power breaker such that it is physically separated from said protective device, for operational data for the power breaker. Data security when using the additional electronic memory is increased by the electronic memory being connected to the protective device via a data bus, which can be used to transmit control signals for the purpose of activating or deactivating a write protection device of the electronic memory. The data bus is preferably an I2C bus, and the write protection device is controlled by an I/O module which is likewise controlled by the I2C bus.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: November 7, 2006
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Driehorn, Andreas Krauss, Aron-Ernst Musiol, Andreas Pancke, Ilka Redmann, Wolfgang Röhl
  • Patent number: 7130173
    Abstract: The invention relates to a trip assembly for use in an electro-mechanical device, such as a circuit breaker. The trip assembly is used for interrupting the flow of current upon the detection of excess current in a circuit breaker and comprises a trip bar, a stationary armature bracket, a movable armature, and a spring. The movable armature includes a first end coupled to a base portion of the armature bracket, and a trip-actuating surface being disposed proximate a trip finger of the trip bar. The spring is directly coupled at its respective ends to a spring-support portion of the armature bracket and to a spring tab of the movable armature.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: October 31, 2006
    Assignee: Square D Company
    Inventor: David W Barewz
  • Patent number: 7130175
    Abstract: At least one or more terminals of an integrated circuit, such as a low- or high-side driver stage, are protected against transient or over-voltages by two pairs of diodes. A first pair of diodes includes a regular diode (D1 or D1?) and a Zener-diode (ZD1 or ZD1?). A second pair of diodes also includes a regular diode (D2 or D3) and a Zener-diode (ZD2 or ZD3). These diode pairs are looped into the respective circuit and cooperate with an n-channel MOSFET or a p-channel MOSFET to provide the required over-voltage protection, particularly for transmitter/receiver circuits and databus systems especially in motor vehicles.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: October 31, 2006
    Assignee: ATMEL Germany GmbH
    Inventors: Franz Dietz, Lars Hehn, Manfred Klaussner, Anton Koch