Patents Examined by Terrence Willoughby
  • Patent number: 7126808
    Abstract: An apparatus is provided for handling workpieces, such as semiconductor wafers, during semiconductor processing. The apparatus includes a wafer platen having a plurality of channels each extending from a top surface to a bottom surface of the wafer platen, a plurality of lift pins in alignment with the channels, and a mechanism for engaging the lift pins in a loading position of the workpiece, a clamping position of the workpiece so that desired semiconductor processes may be performed to the workpiece, and a lift off position for removing the workpiece from the wafer platen after the semiconductor processes are completed. The mechanism places the lift pins below the surface of the wafer platen in the load position and then raises the lift pins to a first predetermined distance above the surface of the wafer platen in the clamp position such that the first predetermined distance allows the workpiece to be clamped to the wafer platen.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: October 24, 2006
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Bon-Woong Koo, Bjorn O. Pedersen, Jay T. Scheuer, Erik A. Mitchell
  • Patent number: 7116537
    Abstract: A surge current prevention circuit and DC power supply for preventing surge current in various operation applications with a small circuit configuration. A power switch connects an external power supply and a load. A first PMOS transistor is connected to a constant current supply. A second PMOS transistor, which forms a current mirror, is connected to a first and second NMOS transistor. A third PMOS transistor is connected to the first and second NMOS transistor, a third NMOS transistor, and fourth and fifth NMOS transistors. A control input is connected to the third NMOS transistor. The first NMOS transistor is connected to the fourth NMOS transistor. An external power supply is connected to the second NMOS transistor. The load is connected to the fourth NMOS transistor.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: October 3, 2006
    Assignee: Freescale Semiconductor, INC
    Inventor: Hiroyuki Kimura
  • Patent number: 7110226
    Abstract: A power supply apparatus has a regulator and a regulator protection circuit. On detecting an abnormality, an abnormality detection circuit in the regulator protection circuit turns the regulator off. Based on the output of the abnormality detection circuit, an abnormality detection incidence checking circuit in the regulator protection circuit checks whether or not an abnormality has been detected a predetermined number of times within a predetermined length of time. When the abnormality detection incidence checking circuit recognizes that an abnormality has been detected the predetermined number of times within the predetermined length of time, an abnormality detection level setting circuit in the regulator protection circuit decreases the detection level of the abnormality detection circuit. This helps reduce the incidence of malfunctioning of the load to which the regulator feeds its output due to repeated detection of an abnormality and recovery therefrom.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: September 19, 2006
    Assignee: Rohm Co., Ltd.
    Inventors: Koichi Inoue, Masahito Kondo
  • Patent number: 7110229
    Abstract: An ESD protection circuit for low temperature poly-silicon thin film transistor panel and a display panel using the same. The feature of the ESD protection circuit comprises an ESD detection circuit disposed between a first power line and a second power line, for outputting an enable signal when an ESD event occurs in the first power line; and a discharge device having a control terminal coupled to the output of the ESD detection circuit, for providing a discharge path between the first and second power lines when the control terminal receives the enable signal.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: September 19, 2006
    Inventors: Sheng-Chieh Yang, An Shih, Ming-Dou Ker, Tang-Kui Tseng
  • Patent number: 7102872
    Abstract: An ESC (Electrostatic Chuck) to chuck an object by electrostatic force, having an ESC main body supporting the object; a guide ring supported by the ESC main body and encircling the object; a dielectric material layer interposed between the guide ring and the ESC main body; a media gas supplier to supply a media gas to the guide ring; and a power supplier to supply power to the ESC main body. With this configuration, the ESC provides an apparatus to chuck a guide ring to an ESC main body, while maintaining the guide ring and an object, such as a wafer, at the same or similar temperature, thereby enhancing uniformity of the object during a semiconductor manufacturing process such as etching, deposition, or the like.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: September 5, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-yong Cho, Byeong-sun An, Jin-man Kim, Kyung-sun Kim
  • Patent number: 7099131
    Abstract: A surge absorber includes a laminated compact of a first ceramic green sheet having a first internal electrode film extending to both sides thereof, a second ceramic green sheet having an second internal electrode film extending to both end surfaces thereof, and a third ceramic green sheet having a discharge hole. Ground external electrode layers are provided on both sides of the laminate so as to be connected with both ends of the first internal electrode film, and signal external electrode layers are further provided on both end surfaces of the laminated compact so as to be connected with both ends of the second internal electrode film. The laminated compact may also include a resistance element.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: August 29, 2006
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toru Tominaga, Makoto Matsubara, Yukichi Sakurai, Takaaki Ooi
  • Patent number: 7099128
    Abstract: A circuit protects a power conversion system with a feedback control loop from a fault condition. The circuit has an oscillator having an input for generating a signal with a frequency and a timer connected to the oscillator input and to the feedback control loop. The timer disables the oscillator after a period following the opening of the feedback control loop to protect the power conversion system.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: August 29, 2006
    Assignee: Power Integrations, Inc.
    Inventors: Balu Balakrishnan, Alex Djenguerian, Leif Lund
  • Patent number: 7075762
    Abstract: In order to enable overheat protection and overcurrent protection as well as temperature detection of an inverter circuit, an inverter circuit comprises a switching circuit 9 composed of a plurality of switching elements and a control circuit 1 for generating a control signal to be inputted into a drive circuit 2 to control a load, a temperature detecting element 12 for detecting a change in temperature of the inverter circuit is provided in a temperature detection circuit 10, and a temperature detection signal which changes according to a change in temperature of said inverter circuit, an overheat abnormal signal outputted upon a rise in temperature to a predetermined temperature or more, and an overcurrent abnormal signal outputted from an overcurrent protection FET 13 are outputted via one commonly used terminal.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: July 11, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Junichi Iimura, Katsumi Okawa, Yasuhiro Koike, Soichi Izutani
  • Patent number: 7072164
    Abstract: An electric parts drive circuit has: a first field-effect transistor including in parallel a first parasitic diode and provided between the plus line and an electric part; a second field-effect transistor including in parallel a second parasitic diode, the first and second field-effect transistors being connected in series in order from the plus line to the electric part; a third field-effect transistor including in parallel a third parasitic diode and provided between a minus line and the electric part; a failure diagnosis switch unit; and a switch control unit, wherein the switch control unit diagnoses a failure of the second field-effect transistor based on the voltage between the first and second field-effect transistors responsive to switching between conduction and shutoff of the second field-effect transistor in a state that the first and third field-effect transistors are shut off and the failure diagnosis switch unit is brought into conduction.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: July 4, 2006
    Assignee: Nissin Kogyo Co., Ltd.
    Inventors: Junichi Amada, Tomoharu Tuchiya
  • Patent number: 7061740
    Abstract: A system and method for protecting an output transistor in an audio amplifier output stage includes a protection circuit that protects the output transistor from excessive currents and voltages, and does not interfere with the normal operation of the output transistor. The protection circuit generates an estimate of the power dissipated by the output transistor, applies this estimate to an electrical analog of the thermal time constants of the transistor to obtain an estimate of the temperature differential between junction and case, compares this differential to a limit, which is a function of transistor case temperature.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: June 13, 2006
    Assignee: Gibson Guitar Corp.
    Inventor: Eric Mendenhall
  • Patent number: 7046109
    Abstract: The present invention relates to a multi-contact type relay in which power is supplied to a load through a BCM (Body Control Module) in accordance with a switching signal from an integration switch, and two coils provided in a relay are selectively activated in accordance with a switching signal from the BCM, so that a fixed contact unit operates based on various contact types in accordance with a movement of a switching part. Therefore, it is possible to fabricate a product as a module, thus resulting in cost reduction and a lightness of a product fabricated thereof.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: May 16, 2006
    Assignee: Hyundai Motor Company
    Inventor: Jong Chan Lee