Patents Examined by Terry D. Cunningham
  • Patent number: 7256638
    Abstract: The apparatus includes a series active continuous time voltage regulator operating in conjunction with a alternating current power source and one or more loads. The alternating current power source is a voltage source that induces currents at a first end of the apparatus. At a second end of the apparatus one or more loads consume power from the apparatus. The series buck-boost regulator is composed of a pure monochromatic voltage source of frequency equal to that of the alternating current power source, and of constant phase with respect to the alternating current power source. The regulator is further composed of a sampling network that provides a scaled continuous time sample of the voltage delivered by the power conditioner to the loads. Finally, the regulator is composed of a high gain differential amplifier.
    Type: Grant
    Filed: February 7, 2002
    Date of Patent: August 14, 2007
    Inventor: Michael Wendell Vice
  • Patent number: 7148739
    Abstract: A charge pump stage comprising a pulse train which injects energy into a gate of a charge transfer transistor of the charge pump stage, wherein a modified output of the pulse train is input to a bulk of the charge transfer transistor such that a bulk voltage of the charge transfer transistor is raised to a level not greater than the minimum of a source voltage and a drain voltage of that charge transfer transistor. A method for operating the charge pump stage is also disclosed.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: December 12, 2006
    Assignee: Saifun Semiconductors Ltd.
    Inventors: Joseph S. Shor, Eduardo Maayan
  • Patent number: 7135910
    Abstract: A charge pump includes a plurality of capacitors that are alternately charged and serially coupled. When serially coupled, the voltage across a given capacitor will equal the voltage at its negative terminal and the voltage across the preceding capacitor.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: November 14, 2006
    Assignee: SanDisk Corporation
    Inventor: Raul-Adrian Cernea
  • Patent number: 7113025
    Abstract: A bandgap reference voltage generating circuit includes a proportional to absolute temperature (PTAT) voltage generating means generating a PTAT voltage. A complementary to absolute temperature (CTAT) voltage generating means generates a CTAT voltage. A temperature coefficient determining means interconnects the PTAT voltage generating means and the CTAT voltage generating means.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: September 26, 2006
    Assignee: Raum Technology Corp.
    Inventor: Clyde Washburn
  • Patent number: 7113027
    Abstract: A semiconductor integrated circuit device has a boosted-voltage power-supply circuit generating a boosted voltage, an internal circuit being driven with the boosted voltage, and a control circuit controlling the internal circuit by receiving the boosted voltage. The boosted-voltage power-supply circuit has a first output terminal for the internal circuit, and a second output terminal for the control circuit. The boosted voltage output from the second terminal has a specified level regardless of variation in the boosted voltage being output from the first terminal.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: September 26, 2006
    Assignee: Fujitsu Limited
    Inventors: Masafumi Yamazaki, Toshiya Uchida
  • Patent number: 7113016
    Abstract: A DC offset cancellation device is provided, including a baseband circuit, a common mode feedback (CMFB) circuit, a low-pass filter (LPF), and an amplifier. The CMFB circuit is used to set a specific common mode DC voltage in a differential circuit; thus, the CMFB circuit can be used for detecting the common mode voltage of a differential circuit, and force the voltage to a specific value by using a feedback control. Because the size of a typical CMFB circuit is much smaller than the size of an LPF, the final size of the one-LPF device is smaller than the conventional design using two LPFs.
    Type: Grant
    Filed: December 11, 2004
    Date of Patent: September 26, 2006
    Assignee: MuChip Co., Ltd
    Inventors: Yong-Hsiang Hsieh, Wen-Kai Li, David Jan-Chia Chen
  • Patent number: 7109779
    Abstract: A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: September 19, 2006
    Assignees: Renesas Technology Corp., Northern Japan Semiconductor Technologies, Inc.
    Inventors: Shigemitsu Tahara, Daisuke Katagiri, Takeshi Shimanuki, Masashi Oshiba
  • Patent number: 7106129
    Abstract: A threshold compensating circuit generates a bias potential VBIAS, that is, a threshold voltage of a MOS transistor offset by a given value. A gate-source voltage having compensation for variation in threshold voltage is thus applied to a transistor. By using a differential amplifier having this transistor as a current source, a voltage down-converter less susceptible to variation in threshold voltage caused by process variation and temperature can be implemented.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: September 12, 2006
    Assignee: Renesas Technology Corp.
    Inventor: Hiroaki Nakai
  • Patent number: 7102408
    Abstract: An information processing apparatus is constructed by a system PLL, a first unit, a second unit, and a system board on which they are mounted. A delay setting circuit in which a variation and delay elements (a gate delay and a line delay) which are equivalent to those of a clock tree circuit for a gate have been set at the designing stage is provided on a signal line of a system clock in the first unit to the second unit. A delay setting circuit in which a variation and delay elements which are equivalent to those of the clock tree circuit for the gate have been set at the designing stage is provided on a signal line of a clock gate signal to the second unit.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: September 5, 2006
    Assignee: Fujitsu Limited
    Inventor: Kazue Yamaguchi
  • Patent number: 7102422
    Abstract: The semiconductor booster circuit includes a plurality of stages, each of which has a MOS transistor and two capacitors. The MOS transistor, having a drain, a source and a gate, is formed in a well of a substrate portion. One capacitor has a terminal connected to the drain of the MOS transistor, while the other capacitor has a terminal connected to the gate of the MOS transistor. A first clock signal generating means generate a first clock signal via another terminal of one capacitor. A second clock signal generating mean s generate a second clock signal, with a larger amplitude than a power supply voltage, via another terminal of another capacitor. The plurality of stages are cascaded together, and in each of the stages the source of the MOS transistor is electrically connected to the well in which the transistor is formed, while the wells are electrically insulated from each other.
    Type: Grant
    Filed: April 18, 1995
    Date of Patent: September 5, 2006
    Assignee: Nippon Steel Corporation
    Inventors: Kikuzo Sawada, Yoshikazu Sugawara
  • Patent number: 7102403
    Abstract: A clock recovering circuit for generating an output clock locked to an analog input signal includes: a phase detection unit for receiving the analog input signal and the output clock for generating a phase error signal according to the analog input signal and the output clock; a loop filter coupled to the phase detector for filtering the phase error signal and generating a control signal; a numerically controlled oscillator (NCO) coupled to the loop filter for generating a first clock and an index signal according to the control signal; a delay locked loop (DLL) coupled to the NCO for receiving the first clock and generating a plurality of second clocks; and a multiplexer coupled to the NCO and the DLL for selecting one of the second clocks as the output clock according to the index signal.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: September 5, 2006
    Assignee: Mediatek Incorporation
    Inventor: Ping-Ying Wang
  • Patent number: 7102423
    Abstract: A voltage boosting circuit and a method of generating a boosting voltage alleviate deterioration of a driver transistor caused by high voltage stress when the level of an external supply voltage is high. The voltage boosting circuit includes boosting capacitors and switches. The boosting capacitors include a first boosting capacitor connected to a driving node and a last boosting capacitor that outputs the boosting voltage. The switches connect the boosting capacitors in series in response to a control signal. The boosting voltage increases or decreases as the voltage level at the driving node changes according to the logic state of a boosting level control signal. The boosting level control signal is responsive to the external supply voltage level. An external supply voltage detector detects the level of external supply voltage level and generates the boosting level control signal.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: September 5, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hoon Lee, Jae-Yoon Sim
  • Patent number: 7102418
    Abstract: The invention relates to a method and an apparatus for producing a reference voltage that is applied to reference voltage inputs on receiver units in order to discriminate between the logic states of a data signal that is transmitted to a receiver end. A transmission device transmits, in addition to the data signal, a clock signal to the receiver end. The receiver end has, on the output side of a receiver unit that receives the clock signal, an integrator that integrates the clock signal and produces the reference voltage from the integrated value.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: September 5, 2006
    Assignee: Infineon Technologies AG
    Inventor: Aaron Nygren
  • Patent number: 7102402
    Abstract: A circuit for generating and distributing highly accurate and stable clocks on a large integrated die is described. A Digital De-skew System is used to help prevent metastability and dither, provide a wide controllable delay range, and alternate sampling of phase detectors.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Javed S. Barkatullah, Charles Dike
  • Patent number: 7102407
    Abstract: A delay circuit. The delay circuit includes a first circuit, a falling edge delay circuit and a rising edge delay circuit. The first circuit includes a circuit input for receiving a reference signal and a circuit output for outputting a delayed signal. The falling edge delay circuit is coupled to the first circuit to control delay of a falling edge of the reference signal. The rising edge delay circuit is coupled to the first circuit to control delay of a rising edge of the reference signal.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: September 5, 2006
    Assignee: Intel Corporation
    Inventor: Darren Slawecki
  • Patent number: 7102391
    Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: September 5, 2006
    Assignee: Actel Corporation
    Inventors: Shin-Nan Sun, Limin Zhu, Theodore Speers, Gregory Bakker
  • Patent number: 7102395
    Abstract: The power-supply voltage detection circuit to detect that an external power-supply voltage and/or an internal power-supply voltage generated from the external power-supply voltage goes out of predetermined regulation comprises a first comparator for detecting the internal power-supply voltage being equal to or less than a predetermined value, a second comparator for detecting the internal power-supply voltage being greater than a predetermined value, a first capacitor for AC-coupling one of the input terminals of the first comparator to the external power-supply voltage, and a second capacitor for AC-coupling one of the input terminals of the second comparator to the external power-supply voltage.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: September 5, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Hirofumi Saito
  • Patent number: 7102424
    Abstract: A reference ladder is configured to have improved feedback stability. The reference ladder includes a resistor ladder having a plurality of taps that produce a plurality of reference voltages. The resistor ladder is driven by a first current source at a first tap of the plurality of taps and by a second current source at a second tap of the plurality of taps. A first feedback network senses a voltage at the first tap and controls the first current source based on the first sensed voltage. A second feedback network senses a voltage at the second tap and controls the second current source based on the second sensed voltage. The first and second taps each operate as both a force tap and a sense tap of the resistor ladder. Differential input stages that are connected to the plurality of taps are at least partially isolated from the feedback networks by converging the force and sense taps, thereby improving the stability of the feedback networks.
    Type: Grant
    Filed: February 14, 2005
    Date of Patent: September 5, 2006
    Assignee: Broadcom Corporation
    Inventor: Pieter Vorenkamp
  • Patent number: 7098709
    Abstract: This invention provides a clock generator which is capable of improving modulation accuracy without accompanying an increase in consumption current by steady current when spectrum spread of a clock signal is executed. The phase balanced voltage Vf to be inputted to the voltage control oscillator (VCO) 9 is modulated within a dead band region in which no difference signals Pr, Pr are outputted from the charge pump circuit 7 when a difference in oscillation frequency between an output clock signal fo and a reference clock signal fr is detected. Consequently, the output clock signal fo is changed within the range of a lock frequency in a PLL circuit, so as to execute the spectrum spread of the output clock signal fo while maintaining the lock state of the oscillation frequency in the PLL circuit.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: August 29, 2006
    Assignee: Fujitsu Limited
    Inventors: Takaaki Ido, Koji Okada, Tomonobu Miyata
  • Patent number: RE39918
    Abstract: A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the summing node. Each current source supplies a current to the summing node wherein the summing node voltage level is responsive to the currents supplied. The indicator circuit is responsive to changes in the summing node voltage level and generates at an output a logical signal at one state when the summing node voltage level is greater than a predetermined value and generates the logical signal at the output at another state when the summing node voltage level is less than the predetermined value, the predetermined value corresponding to a preselected power supply voltage.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: November 13, 2007
    Assignee: STMicroelectronics, Inc.
    Inventor: William Carl Slemmer