Abstract: A multi-phase clock signal generator provides multiple clock signals from an input clock signal, the multiple clock signals being inverted from one another and having substantially the same delay and duty cycle characteristics. Methods of generating multiple clock signals are also provided.

Abstract: In a VDD detect circuit, the output driver interfaces are disabled during power up by pulling the gates of the PMOS interface transistors high using a additional circuitry that operates when VDD is not asserted. The circuit includes a level shifter for controlling the PMOS and NMOS interface transistors during normal mode, and the additional circuitry includes an inverter and a diode string powered by VDDIO, that provides a reference voltage to the level shifter during power up mode. Current flow through the diode string is disabled by a PMOS transistor controlled by VDD, and current flow through the inverter is disabled by the PMOS transistor of the inverter, which is also controlled by VDD. Thus, the additional circuitry provides the enable signal during power up when VDD is not asserted, and does so without causing additional power consumption during normal mode, since the PMOS transistors prevent additional current flow when VDD is high.

Abstract: A switching point detection circuit for detecting a switching point according to a fabrication condition of a MOS transistor includes a reference voltage generation circuit for generating a reference voltage, a first CMOS inverter circuit for receiving the reference voltage, and a second CMOS inverter circuit for receiving the reference voltage, wherein an NMOS transistor is a dominant transistor for the reference voltage in the first CMOS inverter circuit and a PMOS transistor is a dominant transistor for the reference voltage in the second CMOS inverter circuit.

Abstract: A constant-voltage circuit uses a capacitor having a low ESR (equivalent serial resistance), such as a ceramic capacitor, for phase compensation, wherein a voltage drop of an output voltage due to a resistance provided for optimizing the phase compensation is compensated for by providing output current to an output a current proportional to an voltage detecting resistance through a current mirror circuit thereby the voltage drop of the output voltage is compensated for.

Abstract: Well bias voltages are generated in accordance with a logic power supply voltage and a memory power supply voltage. The transistor included in a control circuit in a memory core is constituted of a logic transistor manufactured through the same manufacturing steps as those for the transistors of a logic formed on the same semiconductor substrate. Well bias voltages (VBB, VPP) are applied to a back gate of this logic transistor. A memory integrated with a logic on a common semiconductor substrate is provided which allows a transistor of a control circuit therein to be manufactured through the same manufacturing process as that of the logic and allows reduction of current consumption.

Abstract: In a Dickson type charge pump in which a plurality of serially connected diodes sequentially respond to anti-phase 50/50 clock cross over or overlapped (?1, ?2), efficiency of the charge pump is increased by providing with each diode a charge transfer transistor in parallel therewith between two adjacent nodes, and driving the charge transfer transistor to conduction during a time when the parallel diode is conducting thereby transferring any residual trapped charge at one node through the charge transfer transistor to the next node. Operating frequency can be increased by providing a pre-charge diode coupling an input node to the gate of the charge transfer transistor to facilitate conductance of the charge transfer transistor, and by coupling the control terminal of the charge transfer transistor to an input node in response to charge on an output node to thereby equalize charge on the control terminal and on the input node during a recovery period.

Abstract: A pre-driver circuit for use in high speed signaling systems is disclosed. In one particular exemplary embodiment, the pre-driver circuit may comprise an input transistor, an active load, a passive load, and a current source. The input transistor has a gate terminal, a current sinking terminal, and a current sourcing terminal. The active load has a control input coupled to the gate terminal of the input transistor, a current sourcing terminal coupled to the current sinking terminal of the input transistor, and a current sinking terminal. The passive load has a first terminal coupled to the current sinking terminal of the active load and a second terminal coupled to the current sourcing terminal of the active load. The current source is coupled to the current sourcing terminal of the input transistor.

Abstract: There is provided a reset circuit for reducing current consumption during resetting. A reset circuit 20 is constituted in such a manner that a pulse generation circuit 22 for generating a reset pulse signal (PRSTN) 50 from a reset signal input to an input terminal (RSTN) is connected to a plurality modules 10, 12, 14, a register 40 arranged in the module 10 is initialized based on the reset pulse signal (PRSTN) 50, a register 42 arranged in the module 12 of a next stage is initialized based on a module reset signal (MRSTN) 60 output from a control circuit 30 arranged in the module 10 of a previous stage, and a register 44 arranged in each of modules of stages thereafter, e.g., the module 14, is initialized based on a module reset signal (MRSTN) output from a control circuit 32 arranged in the module 12 of a previous stage.

Abstract: An AC current booster for high speed, high frequency applications having a single-ended output embodiment and a differential output embodiment. The embodiments of the present invention allow bifurcated control of the AC switching rate and the DC state of a given output signal, in order to achieve faster rising and falling edge rates without an undesirable increase in output voltage swing.

Abstract: A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Abstract: A voltage detection circuit for detecting the voltage level of a first power source. A first transistor includes a first gate, a first source, and a first drain coupled to the first gate. A second transistor includes a second gate, a second source, and a second drain coupled to the second gate. A comparator includes a first input terminal, a second input terminal coupled to the second drain, and an output terminal. A first resistor is coupled between the first input terminal and the first drain. A second resistor is coupled to the first power source. A third resistor is coupled between the second resistor and the first input terminal. A fourth resistor is coupled between the second resistor and input terminal. A fifth resistor is coupled between the first source, and a second power source. A resistive device is coupled between the first source, and the first power source.

Abstract: An inrush circuit for electronic devices is particularly useful for point-of-sale printers. The circuit applies an active feedback-controlled voltage ramp to a bulk capacitor by means of a P-channel field effect transistor that is operated linearly after a controlled delay for contact bounce.

Abstract: According to one embodiment, a locally regulated circuit regulates current flows (IREG and IRG) through the operation of a current mirror (334, 332, 326). The regulated current flows are used to self-generate a common mode voltage (V422) at node (322) and to produce the required bias signals through input stage (302 and 308) and output stage (314 and 316) in response to data input signals (D and D-complement). Cancellation of common mode voltage variation is further enhanced by generating a supplemental current in response to an error signal generated by comparing a desired common mode voltage (VCM) to the actual common mode voltage at node (322). The supplemental current conducted by either of loads (310 and 312) serves to regulate the common mode voltage at node (322).

Abstract: A first conductive transistor having a high threshold value and a second conductive transistor having a low threshold value are connected in series between a first actual power supply line supplying a power supply voltage and a virtual power supply line connected to a power supply pin of a circuit block constituted of transistors having a low threshold value. The first and second conductive transistors have polarities which are opposite to each other. A power control circuit turns on the first and second conductive transistors while the circuit block is in operation and turning off the first and second conductive transistors while the circuit block is not in operation. Therefore, subthreshold currents of the first and second conductive transistors can be suppressed. As a result of this, it is possible to reduce power consumption of the semiconductor integrated circuit during its standby period.

Abstract: A charge pump is disclosed which generates higher and more symmetric source and sink currents that prior designs and reduces the multiple frequency sidebands that occur in a voltage controlled oscillator of a phase-loop synthesizer. Other improvements are the reduction in reference frequency feed-through, charge sharing and noise transient coupling and phase noise in the phase-locked loop. Possible applications include but are not limited to charge pump phase-locked designs for single chip CMOS multi-band and multi-standard radio frequency integrated circuits.

Abstract: A self-regulating current source is formed by a PMOS current mirror and an interconnected pair of NMOS transistors. The NMOS transistors are sized differently and forced to operate at similar currents. The difference of the Vgs voltages of the NMOS transistors is impressed across the resistor to develop a stable output current. In particular, the current source starts reliably at low supply voltages and operates to reliably generate a stable low output current at a well-controlled operating point. The self-regulating current source can be used effectively as the watchdog current source of a power-on reset circuit to ensure reliable and robust operation even at low Vdd voltage values.

Abstract: An IC device has a MOSFET serving as a power switch, a condenser connected between a first input terminal of the IC and the gate of the MOSFET, and a ferroelectric condenser connected between a second input terminal of the IC and the gate of the MOSFET. A prescribed voltage having a predetermined polarity is applied across the first and the second input terminals to generate a remanent polarization oriented in a specific direction in the ferroelectric condenser, thereby raising the threshold voltage of the MOSFET to a higher level than its original level. The power switching MOSFET is fabricated in the same manufacturing process as for other circuit blocks of the IC device such that it has substantially the same threshold voltage as that of the MOSFETs in other circuit blocks.

Abstract: A stabilization component for substrate potential regulation for an integrated circuit device. A comparator is coupled to a charge pump to control the charge pump to drive a substrate potential. A stabilization component is coupled to the comparator and is operable to correct an over-charge of the substrate by shunting current from the substrate.

Abstract: A semiconductor integrated circuit device capable of avoiding noise generation and suppressing occurrence of an erroneous operation. Provided is a current limiting circuit where a current flowing in an output terminal of a charge pump circuit is sensed with a sensing resistor to be detected by a current detecting circuit to thereby cause an input current to constantly flow in an input terminal of the charge pump circuit in an amount approximately twice larger than an output current, whereby a current is kept constant to suppress a peak current and to avoid the noise generation. Consequently, other circuits connected to an input power source shared with the charge pump circuit are kept from erroneously operating.

Abstract: A voltage buffer for capacitive loads isolates the load from the feedback loop. Using a variation of a follower arrangement, a second transistor outside of the feedback loop introduced. The current to the load is supplied through the second transistor, which is connected to have the same control gate level as the transistor in the feedback loop and provide an output voltage based on the reference input voltage. The output voltage is dependent upon the input voltage, but the load is removed from the feedback loop. By removing the load from the feedback loop, the loop is stabilized with only a very small or no compensating capacitor, allowing the quiescent current of the buffer to be reduced and the settling time to be improved. One preferred use of the present invention is to drive the data storage elements of a non-volatile memory.