Abstract: A current source DAC has calibration of the current sources used for providing the analog output. There are two outputs, one of which provides the output current or else a differential output is provided. The calibration is cyclic and the current source outputs switched to the output terminals are selected as a function of the point within the calibration cycle. The current stage of the cyclic calibration process is thus taken into account in the D/A conversion. For example, the average time since calibration for all current sources having outputs switched to the first output may be approximately equal to the average time since calibration for all current sources having outputs switched to the second output. In this way, the average current of the cells switched to one terminal is identical to the average current of the cells switched to the other terminal, and the average current of the cells switched to each terminal remains constant in time irrespective of the digital signal value being converted.

Abstract: A bandgap reference voltage circuit includes a constant-current circuit, a reference voltage output circuit generating a reference voltage according to the constant current, a power supply voltage detection circuit, and a start-up output circuit. The start-up output circuit supplies a starting potential to the constant-current circuit until the power supply voltage detection circuit detects that the power supply has reached a voltage sufficient for the constant-current circuit to maintain operation. The power supply voltage detection circuit has elements analogous to the elements in the constant-current circuit that determine this voltage, so start-up operation can occur and end reliably. The start-up output circuit includes a low-impedance path from the power supply to a node controlling supply of the starting potential, so power-supply noise does not trigger unwanted output of the starting potential after start-up operation has ended.

Abstract: Provided is directed to an internal supply voltage generator for a delay locked loop circuit which can prevent a tAC for a next read command from being outputted with a delay, by blocking a supply voltage VDLL from a transient lowering regardless of a reacting speed of a VDLL supply voltage generator by means of maximizing a driving power of the VDLL supply voltage generator which generates the supply voltage VDLL of a delay locked loop during entering time from a power down period to a power up period. Furthermore, as the supply voltage VDLL is prevented from lowering without rising the reacting speed of the VDLL supply voltage generator, it is advantageous to prevent a distorting phenomenon of the supply voltage VDLL in response to a fast reacting speed of the VDLL supply voltage generator.

Abstract: First and second clocks are applied to first and second capacitors, respectively. First and second former-stage clocks are applied to first and second former-stage capacitors, respectively. A first switch couples the second former-stage capacitor with the first capacitor. A second switch couples the first former-stage capacitor with the second capacitor. A first reverse current preventing circuit couples a control electrode of the first switch alternately with the second capacitor and the second former-stage capacitor. A second reverse current preventing circuit couples a control electrode of the second switch alternately with the first capacitor and the first former-stage capacitor. Falling edges of the first and second clocks occur earlier than falling edges of the first and second former-stage clocks, respectively. Rising edges of the first and second former-stage clocks occur earlier than rising edges of the first and second clocks, respectively.

Abstract: The reconfigurable analog cell according to the invention comprises admittances yab having first terminals (a) which are coupled to first terminals SW1 of a first plurality of switches, and having second terminals which are coupled to the first terminals SW1 of a second plurality of switches. The switches having second terminals, wherein each one of the second switch terminals SW2 of the first plurality of switches and of the second plurality of switches is coupled to at least one node of a plurality of nodes. In the arrangement only one of the switches from any plurality is ON. Therewith a particular state of a plurality of possible states (PSPPS) of the RAC (100) is defined, each of the states defining a transfer function having the same set of poles.

Abstract: An apparatus for a multiplexor circuit includes a passgate circuit coupled to receive input signals and corresponding select signals comprising a subset of the input signals and select signals received by the multiplexor. The apparatus also includes a default circuit coupled to receive the select signals and coupled to an output node of the passgate circuit. If none of the select signals is asserted, the default circuit supplies a default voltage on the output node. Other passgate circuits and default circuits may be included coupled to other subsets of the input signals and select signals, and an output circuit may be included with inputs coupled to the output nodes of the passgate circuits. The default voltage may represent a logical value which allows the value from another passgate circuit to control the output of the output circuit.

Abstract: A switch in bipolar technology including a first main transistor of a first type connecting an input terminal, intended to be connected to a first terminal of application of a D.C. supply voltage, to an output terminal intended to be connected to a load to be supplied; a second bipolar transistor of the same type as the first one, connected between the input terminal and an input of a current mirror circuit having a copying output connected to the base of the first transistor, the bases of the first and second transistors being interconnected and the first transistor having an emitter surface area greater than the second one; and a circuit for biasing the second transistor including the copying of the output voltage of the switch on the collector of this second transistor.

Abstract: Disclosed is a synchronous mirror delay circuit for generating an internal clock signal synchronized with an external clock signal, comprising: a clock buffer circuit that generates a reference clock signal in response to the external clock signal; a delay monitor circuit that delays the reference clock signal; a forward delay array for delaying an output clock signal of the delay monitor circuit to generate delay clock signals; a mirror control circuit that receives the delay clock signals and the reference clock signal to detect one delay clock signal synchronized with the reference clock signal among the delay clock signals; a backward delay array that delays the delay clock signal detected by the mirror control circuit to output a synchronous clock signal; a delay circuit that delays an asynchronous clock signal output through the forward delay array; and a clock driving circuit that outputs the delayed asynchronous clock signal as the internal clock signal when the reference clock signal is not synchroni

Abstract: The present invention is to provide a charge pump circuit for improving switching speed and compensating mismatch between a source and a sink currents flowing to output terminal. A charge pump circuit according to the first embodiment of the present invention comprises a first and second switching elements, a discharging and charging elements, a biasing unit, a first and second compensating unit, a charge pumping unit, a current mirror unit, a control unit, and a biasing unit. The compensating circuit removes the deterioration owing to the parasitic capacitance, and the control circuit controls the charge that is flowed or emitted from the parasitic capacitance. A charge pump circuit according to the second embodiment of the present invention comprises a charge pumping unit, a current mirror unit, a control unit a biasing unit. The charge pump circuit decects the mismatch between the output currents via the control unit, and compensates the mismatch by the biasing unit.

Abstract: A voltage ramp generator includes a capacitance and a charging circuit that permits generation of a charging current for the capacitance. The charging circuit for the capacitance includes a current generator having a resistance Rg2. The charging circuit for the capacitance includes components, such as resistance Re, that enables the capacitance charging current to be proportional to (Re/Rg2)2. The voltage ramp generator is applicable to circuits for DC voltage converters operating in a current mode.

Abstract: There is disclosed control circuitry for adjusting a power supply level, VDD, of a digital processing component having varying operating frequencies. The control circuitry comprises N delay cells and power supply adjustment circuitry. The N delay cells are coupled in series, each of which has a delay D determined by a value of VDD, such that a clock edge applied to an input of a first delay cell ripples sequentially through the N delay cells. The power supply adjustment circuitry capable of adjusting VDD and is operable to (i) monitor outputs of at least a K delay cell and a K+1 delay cell, (ii) determine that the clock edge has reached an output of the K delay cell and has not reached an output of the K+1 delay cell, and (iii) generate a control signal capable of adjusting VDD in response thereto.

Abstract: Programmable linear-in-dB or linear bias current source with respect to an input voltage is provided. The linear-in-dB or linear bias current may be clipped at a minimum current level, a maximum current level, or a combination thereof. Preferably, the minimum and maximum current levels are determined by the use of one or more constant current sources. The constant current sources limit the amount of voltage applied to the gates of one or more transistors, which in turn control the output current. The use of the circuit may be used to generate linear or reverse-linear current levels with respect to an input voltage. The output of the current generator may be used as an input to a power-amplifier driver, for example.

Abstract: In a semiconductor integrated circuit device, a first control signal outputted from the power voltage evaluation circuit controls power voltage of the power voltage generation circuit so that the power voltage becomes lower within a range over which the internal circuit normally operates, while a second control signal outputted from the specified voltage detection circuit controls the power voltage of the power voltage generation circuit so that the power voltage generated by the power voltage generation circuit does not become equal to or higher than a specified voltage. This makes the power voltage as low as possible within the normally operational range of the internal circuit and suppresses increase of the gate current, so that unstable operations and current consumption increase of the MOS transistor can be prevented.

Abstract: A semiconductor integrated circuit comprises a power supply voltage step down circuit and a MOS circuit group. The power supply voltage step down circuit is supplied with a power supply voltage and controlled by a standby control signal indicating an operating state or a standby state. The power supply voltage step down circuit outputs a first internal power supply voltage lower than the power supply voltage to an internal power supply line when the standby control signal indicates the operating state, and outputs a second internal power supply voltage lower than the first internal power supply voltage to the internal power supply line when the standby control signal indicates the standby state. The MOS circuit group including one or more MOS transistors which are supplied with the first or second internal power supply voltage from the internal power supply line to operate.

Abstract: The invention provides a method and apparatus for performing a voltage to current conversion. In particular, the invention provides a voltage to current converter configured to vary its transconductance (Gm). Such a converter is configured to receive a voltage input signal combined with a reference voltage signal to be converted to a current output. Optionally, the reference voltage signal may be provided by a parabolic impedance network that includes a bank of resistors and a plurality of corresponding current sources. Each current source corresponds to each node between two resistors, and may be varied in order to program changes in the comparator's Gm. Each resistor and corresponding current source is configured to create an individual reference voltage reference having a value that occurs in a parabolic manner in relation to other voltage references occurring across the impedance network. The converter further includes a plurality of comparators corresponding to the plurality of voltage reference signals.

Abstract: A power-on reset circuit is capable of outputting a normal reset signal despite slow rise of power supply voltage. A node is interposed between a MOS capacitor including a PMOS with its drain and source connected in common and an NMOS having its gate fixedly connected to a ground potential. The node is connected to a ground potential via the NMOS and also to a power supply line via the MOS capacitor. Therefore, even when the power supply voltage rises slowly after power is turned on, the potential of the node rises substantially at the same rate as the power supply voltage. After the power supply voltage reaches a predetermined power supply potential, the potential of the node is gradually lowered due to an off leakage current through the NMOS. The node is connected with an inverter operating according to the power supply voltage. When the potential of the node decreases below ½ of the power supply voltage, the reset signal outputted from the inverter goes to the H level.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: A bias current generating circuit including a bandgap reference circuit which outputs a first voltage which is constant, and a second voltage which changes in accordance with a temperature. The generating circuit also includes a first low-potential-side constant-current source circuit which receives the second voltage, and outputs a first electric current dependent on a temperature, and a second low-potential side constant-current source circuit which receives the first voltage, and outputs a second electric current independent of a temperature. A third low-potential-side constant-current source circuit in the generating circuit receives the first voltage, and supplies a third temperature-independent current. A high-potential-side constant-current source circuit receives a third voltage and outputs a fourth electric current independent of a temperature.

Abstract: Non-iterative introduction of phase delay into a signal, without feedback, is disclosed. A system of one embodiment of the invention includes a controller and a mechanism. The controller provides a pulse having a length representative of a phase delay for introduction into a signal. The mechanism non-iteratively introduces the phase delay into the signal based on the pulse, without feedback.

Abstract: The invention relates to a Polyphase-Notchfilter for filtering input signals comprising known bandpass filters, which comprise voltage-controlled current sources. To provide an integrated circuit that has notch filter functionality with reduced circuit erogation, that allows high suppression with little matching effort and reduced power consumption it is proposed that at least two second voltage-controlled current sources are provided, that said at least four input means are coupled to said at least two second voltage-controlled current sources, and that said at least four output means are coupled to said at least two second voltage-controlled current sources, and that said at least one second voltage-controlled current sources are coupled antiparallel to bandpass filter.