Abstract: A microwave resonant cavity includes a conductive shell with a screw hole having first threads and a screw having second threads configured to engage with the screw hole. The conductive shell defines a volume, the screw extends into the volume, the microwave resonant cavity has a resonant frequency, and the movement of the screw changes the resonant frequency. The first threads have a first pitch, and at least a portion of the second threads has a second pitch different from the first pitch.

Abstract: An integrated circuit die includes multiple temperature sensor units each for measuring the temperature of respective regions of a semiconductor substrate of the integrated circuit die. The temperature sensor units are each coupled to a multiplexer by respective groups of signal lines. The signal lines include resistance compensation areas for maintaining a particular ratio of resistances of the signal lines of each group.

Abstract: A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.

Abstract: An electronic device includes a first circuit, and a delay circuit electrically connected to the first circuit. The delay circuit includes a resistor, a capacitor, and a process, voltage or temperature (PVT) compensation circuit electrically connected to the capacitor.

Abstract: An integrated circuit (IC) including a high-speed signal input pin, a common node, a high-speed signal output pin, and a core circuit is provided. The high-speed signal input pin and the high-speed signal output pin are disposed on a package of the IC. The common node and the core circuit are disposed in the IC. The common node is directly and electrically coupled to the high-speed signal input pin. The high-speed signal output pin is directly and electrically coupled to the common node. A high-speed signal input terminal of the core circuit is directly and electrically coupled to the common node.

Abstract: A voltage detection circuit includes a voltage detection unit suitable for comparing a voltage level of a reference voltage terminal with a voltage level of an internal voltage terminal and for generating a detection signal based on a comparison result, a test reference voltage generating unit suitable for receiving an external reference voltage through a pad and for supplying a test reference voltage, which is generated by using the received external reference voltage, to the reference voltage terminal by using a first input resistance, during a test operation, and a normal reference voltage generating unit having a current mirror structure, wherein the normal reference voltage generating unit is suitable for supplying a current, corresponding to an internal reference voltage, to the reference voltage terminal by using a second input resistance different from the first input resistance, during a normal operation.

Abstract: Internal voltage generation circuits are provided. The internal voltage generation circuit includes a code signal generator and an internal voltage generator. The code signal generator generates input code signals having a logic level combination corresponding to a difference between a frequency of an external clock signal and a frequency of an internal clock signal. The internal voltage generator is selectively activated according to the logic level combination of the input code signals to drive an internal voltage signal.

Abstract: A signal processing device enables a high quality enhanced signal to be obtained, and includes: a transform unit which transforms a mixed signal in which a first signal and a second signal are mixed, into a phase component and an amplitude component or a power component in each frequency; a first control unit which rotates the phase component in a predetermined frequency; a second control unit which compensates the amplitude component or the power component in the predetermined frequency according to the amount of change of the amplitude component or the power component rotated by the first control unit; and a synthesizing unit which synthesizes the phase component rotated by the first control unit, and the amplitude component or the power component compensated by the second control unit.

Abstract: A method and apparatus for current drain switching with a replica loop. The method comprises the steps of: matching a voltage across a current sense resistor with a voltage created by a reference current across a matched reference resistor; replicating an operating point of an output transistor using a scaled matched replica of the output transistor and the current sense resistor. The method then shifts a feedback voltage from the output sense resistor to the matched replica sensor and shifts the output of a gate from an output transistor to the replica transistor. A first switch is then actuated in order to preserve the gate charge of the output transistor. A second switch is actuated to sample and hold a drain voltage in the buffer in order to bias the drain of the replica transistor. A third switch is then activated to stop the output current.

Abstract: A charge pump system uses a helper pump to use in generating a boosted clock signal to use for a capacitor of a stage of a charge pump and also for the gate clock of the stage. This can be particularly useful in applications with lower supply levels, where the helper pump can be used to provide an amplitude higher than the supply level, that can then be added to the supply level for the boosted clock signal and then added again to the supply level for the gate clock. Further advantages can be obtained by using the helper or auxiliary pump as an input to an optimized inverter circuit that receives an input clock and has an output that initially rises to the supply level then subsequently to the auxiliary pump's level.

Abstract: In various embodiments, a switch circuit arrangement may include a switch circuit, a driver circuit and a supply circuit. The driver circuit may be configured to control the switch circuit. The supply circuit may be configured to power the driver circuit. The supply circuit may include a first circuit configured to modify an output impedance of the supply circuit to have a first impedance when the driver circuit controls the switch circuit to be in a conducting state and to have a second impedance when the driver circuit controls the switch circuit to change from a non-conducting state to the conducting state.

Abstract: A port current control arrangement, constituted of: a current source arranged to generate a reference current or a predetermined value; an on-chip reference resistor, the generated reference current arranged to produce a reference voltage across the on-chip reference resistor; an on-chip sense resistor, a port current arranged to flow through the on-chip sense resistor and produce a sense voltage across the on-chip sense resistor, wherein the resistance of the on-chip sense resistor exhibits a predetermined relationship with the resistance of the first on-chip reference resistor; and a current control circuit, a first input of the current control circuit arranged to receive the produced reference voltage and a second input of the current control circuit arranged to receive the sense voltage, wherein the current control circuit is arranged to limit the port current to a value responsive to the received reference voltage and the received sense voltage.

Abstract: Some embodiments relate to charge pump regulators to selectively activate a charge pump based not only on the voltage output of the charge pump, but also on a series of wake-up pulses that are delivered at predetermined time intervals and which are delivered independently of the voltage output of the charge pump. Hence, these wake-up pulses prevent extended periods of time in which the charge pump is inactive, thereby helping to prevent latch-up in some situations.

Abstract: Low-power circuits for providing stable voltage and current references rely on currents flowing through ultra-thin dielectric layer components for operation. A current reference circuit includes driving circuitry operative to apply a voltage to the first terminal of the component with respect to the second terminal of the component in order to cause a current to flow through the dielectric layer, and sources a reference output current that is based on the current flow through the dielectric layer in response to the applied voltage. A voltage reference circuit includes a current source which applies a current to the ultra-thin dielectric layer component, and maintains an output node at a stable reference output voltage level based on the voltage across the ultra-thin dielectric layer component in response to the current flow through the dielectric layer.

Abstract: An integrated circuit device can include at least a first bi-directional biasing circuit having a first substrate portion containing a plurality of first transistors; a first control digital-to-analog converter (DAC) to generate any of a plurality of first target values in response to a first target code; a first detect circuit configured to generate a difference value between the first target values and a first limit value; and at least a first charge pump circuit configured to drive the first substrate portion between a forward body bias voltage and a reverse body bias voltage for the first transistors in response to first target values. Embodiments can also include a performance monitor section configured to determine a difference between the voltage of the first substrate portion and a target voltage. Control logic can generate first code values in response to the difference between the voltage of the first substrate portion and the target voltage. Methods are also disclosed.

Abstract: A method of debouncing a variable frequency step signal is provided. The method includes the steps of: (a) determining a first period in oscillations of the variable frequency step signal and applying a first debounce time to debounce oscillations in the variable frequency step signal, (b) detecting a second period in the oscillations of the variable frequency step signal, (c) calculating a second debounce time as a fraction of the first period, (d) applying the second debounce time to debounce oscillations having the second period, and (e) repeating the steps (b)-(d) for debouncing successive oscillations of varying periods in the variable frequency step signal.

Abstract: An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor.

Abstract: Provided is a reference voltage generation circuit that has a flat temperature characteristic even when there are fluctuations in manufacturing step. After a semiconductor manufacturing process is finished, electrical characteristics of a semiconductor device are evaluated. Temperature characteristic of each reference voltage (VREF) of three unit reference voltage generation circuits (10) is evaluated. Then only a unit reference voltage generation circuit (10) having the most flat temperature characteristics is selected from among the three unit reference voltage generation circuits (10). Only fuses (13, 14) of the selected unit reference voltage generation circuit (10) are not cut, but other fuses (13, 14) are cut. Accordingly only the selected unit reference voltage generation circuit (10) operates, and the other unit reference voltage generation circuits (10) do not operate.

Abstract: Driver circuits (1) for driving load circuits (2, 3) receive source signals from sources and provide feeding signals to the load circuits (2,3) and charging signals to capacitor circuits (21). These capacitor circuits (21) provide supporting signals to the load circuits (2, 3) in addition to the feeding signals. By providing the driver circuits (1) with control circuits (22) for controlling the supporting signals, the capacitor circuits (21) can become less bulky/costly and/or will limit the lifetime of the driver circuits (1) to a smaller extent. Further, these driver circuits (1) may get improved efficiencies. Said controlling may comprise controlling moments in time at which the supporting signals are offered to the load circuits (2, 3) or not, and/or may comprise controlling sizes of the supporting signals, and/or may be done in response to detection results from detectors (23) for detecting parameters of one or more signals. Said controlling may comprise switching via switches (24).

Abstract: A semiconductor chip package eliminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit, and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and a mounting substrate to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package.