Abstract: Configurable flip-flop cells for use in scan chain configurations include one or more multiplexers, a flip-flop, and one or more logic gates. The logic gates are configurable, through modification of different metallization or semiconductor layers, to operate as spare gates or to disable flip-flop cell outputs based selection signal switching between scan shift and capture mode. When disabling flip-flop cell outputs, the logic gates are configured to receive both a test signal and a data input signal and select one of the two to pass to the flip-flop based on the selection signal. When used as spare gates, the logic gates receive external inputs and provide spare gate outputs to circuitry on an integrated circuit that is external to the flip-flop cells.

Abstract: A pre-charging circuit, such as can be used to pre-charge a data bus, is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connected to ground by another transistor. These transistors can be controlled by one or more comparators that have as inputs a reference level and feedback from the output. The reference level is generated by a circuit that tracks the threshold voltage of the other devices in the circuit in order to reduce process dependency of the output level. The circuit can also include a device to provide an extra VDD assist to the output.

Abstract: A direct current offset correction circuit includes an obtaining module, a controller, and a correction module. The obtaining module obtains a DC offset voltage from an output of a target circuit. The controller is connected to the obtaining module, and the controller outputs correction signals in response to the direct current offset voltage being greater than a predetermined voltage. The correction module is connected to the target circuit, the obtaining module, and the controller. The correction module compensates the direct current offset voltage of the target circuit according to the correction signals.

Abstract: A semiconductor device includes a power supply voltage level/slope detection unit configured to detect a level of a power supply voltage and a slope of a power supply voltage curve, and output a power supply voltage level/slope detection signal, a pumping voltage detection unit configured to detect a level of a pumping voltage based on a reference pumping level to output a pumping detection signal, an oscillation signal generation unit configured to generate an oscillation signal in response to the pumping detection signal and the power supply voltage level/slope detection signal, and a pumping unit configured to generate the pumping voltage by performing a charge pumping operation in response to the oscillation signal.

Abstract: Voltage and current mode reconfigurable nth-order filters (RNOFs), fabricated in a 0.18 ?m CMOS process, utilize an inverse-follow-the-leader-feedback (IFLF) signal path with summed outputs, resulting in a follow-the-leader-feedback-summed-outputs (FLF-SO) filter topology. The FLF-SO filter uses multi-output current amplifiers (CAs). Inverse-follow-the-leader-feedback-summed-outputs (IFLF-SO) and inverse-follow-the-leader-feedback-distributed-outputs (IFLF-DI) structures are realized by employing 3n+4 transconductance amplifiers (TCAs) for voltage mode processing and two TCAs for current mode signals. A plurality of programmable current division networks (CDNs) tune a digitally controlled current follower (DCCF). A multi-output Digitally Controlled Current Amplifier (MDCCA) controls gain by providing independent filter coefficient control. Forward path output gains are set to unity. Alternatively, a multi-output digitally controlled CCII block (MDCCCII) uses CCII in the first stage.

Abstract: A stacked chip system is provided to comprise a first chip, a second chip, a first group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one first VSS TSV, at least one first VDD TSV, a plurality of first signal TSVs and at least one first redundant TSV and a second group of through silicon vias (TSVs) connecting the first chip and second chip and comprising at least one second VSS TSV, at least one second VDD TSV, a plurality of second signal TSVs and at least one second redundant TSV, wherein all the first group of TSVs are coupled by a first selection circuitry configured to select the at least one first redundant TSV and bypass at least one of the rest of the first group of TSVs, and wherein the at least one first redundant TSV and the at least second redundant TSV are coupled by a second selection circuitry configured to allow one of them to replace the other.

Abstract: An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: Voltage and current mode reconfigurable nth-order filters (RNOFs) fabricated in a 0.18 ?m CMOS process are disclosed. The RNOFs utilize an inverse-follow-the-leader-feedback (IFLF) signal path with summed outputs, resulting in a follow-the-leader-feedback-summed-outputs (FLF-SO) filter topology. The FLF-SO filter uses multi-output current amplifiers (CAs). Inverse-follow-the-leader-feedback-summed-outputs (IFLF-SO) and inverse-follow-the-leader-feedback-distributed-outputs (IFLF-DI) structures are realized by employing 3n+4 transconductance amplifiers (TCAs) for voltage mode processing and two TCAs for current mode signals. A plurality of programmable current division networks (CDNs) tune a digitally controlled current follower (DCCF). A multi-output Digitally Controlled Current Amplifier (MDCCA) controls gain by providing independent filter coefficient control. Forward path output gains are set to unity. Alternatively, a multi-output digitally controlled CCII block (MDCCCII) uses CCII in the first stage.

Abstract: An antenna drive apparatus having a drive control unit and an antenna connected to the drive control unit via first and second connecting lines, and driven by an AC signal at a first resonant frequency, includes: a first driven member connected to the drive control unit via the connecting lines and driven by the AC signal at a second resonant frequency; a sensing member connected to the drive control unit via the connecting lines and driven by a DC signal, capable of sensing approach or contact of a person and, outputting a sensing signal indicating the fact that the approach or the contact has been sensed to the drive control unit via the first connecting line; and a stop mechanism configured to stop a function of the sensing member when the AC signal supplied to the antenna or the first driven member is sensed.

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a resistive divider comprising a first resistor and a second resistor may be coupled with the FET at a position electrically between a gate terminal of the FET and a body terminal of the FET.

Abstract: A method for generating a reference voltage includes generating a proportional-to-absolute temperature (PTAT) voltage across a first pseudo resistor. The first pseudo resistor includes a transistor. The method also includes converting the PTAT voltage to a current based on a resistance of the first pseudo resistor. The method also includes mirroring the current using a current mirror circuit and converting the mirrored current to a converted PTAT voltage using a second pseudo resistor. The second pseudo resistor includes a transistor. The first pseudo resistor and the second pseudo resistor include equal transistor types. The method also includes generating a complementary-to-absolute temperature (CTAT) voltage, and summing the converted PTAT voltage and the CTAT voltage to produce the reference voltage. The resulting reference voltage is temperature independent.

Abstract: Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly charging and discharging at low voltage operation conditions. Additional aspects may include features that enable state by state pumping, for example, circuitry that avoids cascaded short circuits among pump stages. Each pump stage may also include circuitry that discharges its nodes, such as via self-discharge through associated pump interconnection(s). Further aspects may also include features that: assist power-up in the various pump stages, double voltage, shift high voltage levels, provide anti-parallel circuit configurations, and/or enable buffering or precharging features, such as self-buffering and self-precharging circuitry.

Abstract: Implementations relate to methods and apparatus for the aggregation of guide and frequency map information for multiple frequency networks (MFNs) using an upper-level single frequency network (SFN). A mobile device can provide a program guide displaying a listing of content scheduled for broadcast by a content server. An upper network can be in hierarchical coverage with at least two networks, and can receive at least one of guide and frequency data associated with the program guide from the at least two networks. The upper network can aggregate the at least one of guide and frequency data into aggregated guide and frequency data. The aggregated data can be distributed to the at least two networks and/or accessed from the upper network. The mobile device can receive the aggregated data from either the at least two networks or the upper network.

Abstract: A stack package having a plurality of stacked chips includes first voltage dropping units respectively formed in the plurality of chips, the first voltage dropping units are electrically coupled by a first line; second voltage dropping units respectively formed in the plurality of chips, the second dropping units are electrically coupled by a second line; first signal generation units respectively formed in the plurality of chips, each of the first signal generation units is connected to an output node of the first voltage dropping units, respectively; and second signal generation units respectively formed in the plurality of chips, each of the second signal generation units is connected to an input node of the second voltage dropping units, respectively.

Abstract: A temperature compensation circuit is disclosed. A temperature compensation circuit may include a temperature coefficient generator configured to generate a first signal and a second signal, wherein the first signal is proportional-to-absolute-temperature (ptat) and the second signal is negatively-proportional-to-absolute-temperature (ntat), a first programmable element configured to multiply at a first programmable ratio an amplitude of a third signal having a negative temperature coefficient from a first temperature to a second temperature, and a second programmable element configured to multiply at a second programmable ratio an amplitude of a fourth signal having a positive temperature coefficient from the second temperature to a third temperature.

Abstract: Sallen-Key filters require an operational amplifier with a large input impedance and a small output impedance to meet the external filter characteristics. This invention eliminates the need for internal feedback path for stability and increases the gain of a source follower which has characteristics matching the operational amplifier in the Sallen-Key filter. The source follower provides 6 dB of AC voltage gain and is substituted for the operational amplifier in the Sallen-Key filter. The Sallen-Key filter requires a differential configuration to generate all the required signals with their complements and uses these signals in a feed forward path. Furthermore, since the source follower uses only two n-channel stacked devices, the headroom voltage is maximized to several hundred millivolts for a 1.2V voltage supply in a 40 nm CMOS technology. Thus, the required 880 MHz bandwidth of the Sallen-Key filter can be easily met using the innovative source follower.

Abstract: A reference quantity generator for generating a reference quantity includes a reference source configured to provide a reference source signal, a digitally controlled signal source and a digital controller. The digitally controlled signal source is configured to provide a digitally controlled quantity. The reference quantity is determined based on the digitally controlled quantity. The digital controller is configured to provide a digital control signal to control the digitally controlled signal source to adapt the digitally controlled quantity based on the reference source signal using a feedback.

Abstract: System and methods are provided for signal processing. For example, an input signal is received at a finite impulse response filter circuit including a plurality of stages, where each stage of the plurality of stages is associated with a sample value of the input signal and a stage weight. An output signal is generated using the finite impulse response filter circuit, the output signal being equal to a weighted sum of the sample values of the input signal. An error signal is generated to indicate a difference between the output signal and a target. A constraint is applied to one or more of the stage weights. The stage weights are changed within the constraint to reduce a magnitude of the error signal.

Abstract: A system and method for operating a power transistor. Parasitic impedances naturally present in a circuit board or other interconnect structures exhibit a parasitic impedance effective to generate a parasitic voltage signal in response to operating the power transistor. The parasitic voltage signal is monitored in order to better control the power transistor. In particular, the threshold voltage of the power transistor can be determined and used to more optimally control the power transistor.