Patents Examined by Thao Le
  • Patent number: 8994062
    Abstract: A LED module includes a substrate, a LED chip supported on the substrate, a metal wiring installed on the substrate, the metal wiring including a mounting portion on which the LED chip is mounted, an encapsulating resin configured to cover the LED chip and the metal wiring, and a clad member configured to cover the metal wiring to expose the mounting portion, the encapsulating resin arranged to cover the clad member.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: March 31, 2015
    Assignee: Rohm Co., Ltd.
    Inventor: Masahiko Kobayakawa
  • Patent number: 8735872
    Abstract: An organic light emitting diode (OLED) display includes: a substrate including a first area and a second area; a first electrode at the first area of the substrate, and a first electrode at the second area of the substrate; a reflective electrode on the first electrode at the first area; a barrier rib on the substrate, the barrier rib having openings exposing the reflective electrode and the first electrode at the second area; an organic emission layer on the reflective electrode and the first electrode at the second area; a second electrode on the organic emission layer; and a reflective layer on the second electrode at the second area.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae-Gon Kim, Chul-Woo Jeong, Chi-Wook An
  • Patent number: 8729552
    Abstract: In one aspect, a back plane for a flat panel display apparatus include: a substrate; a source electrode and a drain electrode formed on the substrate; a capacitor bottom electrode formed on a same layer as the source/drain electrodes; an active layer formed on the substrate in correspondence to the source electrode and the drain electrode; a blocking layer interposed between the source electrode and the drain electrode and the active layer; a first insulation layer formed on the substrate to cover the active layer; a gate electrode formed on the first insulation layer in correspondence to the active layer; a capacitor top electrode formed on a same layer as the gate electrode in correspondence to the capacitor bottom electrode; and a second insulation layer formed on the first insulation layer to cover the gate electrode and the capacitor top electrode is provided.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: May 20, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang-Suk Kim, Min-Kyu Kim
  • Patent number: 8723150
    Abstract: A semiconductor memory device according to an embodiment comprises a semiconductor layer, a variable resistance layer, a sidewall layer, and a buried layer. The semiconductor layer functions as a rectifying device. The variable resistance layer is provided above or below the semiconductor layer and reversibly changes its resistance. The sidewall layer is in contact with a sidewall of the semiconductor layer. The buried layer is embedded in the sidewall layer and is made of material different from that of the sidewall layer. These configurations may adjust the electrical characteristics of the rectifying device to any value.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Sonehara
  • Patent number: 8716099
    Abstract: A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 6, 2014
    Assignee: Higgs Opl. Capital LLC
    Inventor: Frederick T. Chen
  • Patent number: 8716834
    Abstract: A semiconductor device that can prevent reduction in the amplitude of electromagnetic waves transmitted from a reader/writer, and can prevent heating of an element forming layer due to a change in a magnetic field. The semiconductor device of the invention has an element forming layer formed over a substrate, and an antenna connected to the element forming layer. The element forming layer has at least wires such as a power supply wire and a ground wire that are arranged in a non-circular shape. The element forming layer and the antenna may be provided so as to overlap each other at least partially. The antenna may be provided above or below the element forming layer.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: May 6, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyoshi Kato, Yoshitaka Moriya
  • Patent number: 8716750
    Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: May 6, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Teng-Chun Hsuan, I-Ming Lai, Chin-Cheng Chien
  • Patent number: 8710574
    Abstract: A memory cell including: an active area having a channel provided between a source and a drain, a first gate provided on a first part of the channel, a portion of a first lateral spacer provided against a lateral flank of the first gate, a part of which forms a second gate provided on a second part of the channel, one of two gates forming a storing gate, the memory cell further including a portion of a second lateral spacer provided against a lateral flank of a block provided on the semi-conductor layer, the second lateral spacer being in contact with the first lateral spacer, the first and second lateral spacers being composed of similar materials, said portion of the second lateral spacer forming a part of an electrical contact pad electrically connected to the second gate.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: April 29, 2014
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Marc Gely, Gabriel Molas
  • Patent number: 8711933
    Abstract: A random access point can be generated in a stream of coded digital pictures containing a plurality of predictive coded frames in which one or more subsections of each frame are intra coded. A patch frame can be formed from intra-coded subsections in identified consecutive predictive-coded frames. The patch frame can be used as a synthetic random access point.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: April 29, 2014
    Assignee: Sony Computer Entertainment Inc.
    Inventor: Hung-Ju Lee
  • Patent number: 8710568
    Abstract: A semiconductor device includes a semiconductor substrate that includes a plurality of section having different thicknesses. The sections include a first section having a first thickness and a second section having a second thickness, the second section is the thinnest section among all the sections, and the first thickness is greater than the second thickness. A plurality of isolation trenches penetrates the semiconductor substrate for defining a plurality of element-forming regions in the first section and the second section. A plurality of elements is located at respective ones of the plurality of element-forming regions. The elements include a double-sided electrode element that includes a pair of electrodes separately disposed on the first surface and the second surface, and the double-sided electrode element is located in the second section.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: April 29, 2014
    Inventors: Yoshihiko Ozeki, Tetsuo Fujii, Kenji Kouno
  • Patent number: 8709881
    Abstract: A substrate is provided that has a metallic layer on a substrate surface of a substrate. A film made of a two dimensional (2-D) material, such as graphene, is deposited on a metallic surface of the metallic layer. The metallic layer is dewet and/or removed to provide the film on the substrate surface.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: April 29, 2014
    Assignee: The Regents of the University of California
    Inventors: Yuegang Zhang, Ariel Ismach
  • Patent number: 8703601
    Abstract: Disclosed are an application method, device and program which enable the constant retention of a fillet shape, without altering the shape due to the speed differences associated with changes in the direction of the nozzle or differences in the degree of penetration when bumps are arranged non-uniformly. In a liquid material application method a desired application pattern is created, liquid material is discharged from a nozzle whilst the nozzle and a workpiece are moved relative to one another, and the gap between a substrate and the workpiece, the workpiece being placed above the substrate by means of at least three bumps, is filled up with liquid material by capillary action. If bumps are arranged non-uniformly, the supply quantity per unit area of the application pattern is set so that a greater quantity is supplied to application areas next to areas where the integration density of bumps is high, than is supplied to application areas next to areas where the integration density of bumps is low.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: April 22, 2014
    Assignee: Musashi Engineering, Inc.
    Inventor: Kazumasa Ikushima
  • Patent number: 8697536
    Abstract: A method of fabricating a semiconductor device comprises forming a plurality of trenches in a bulk semiconductor substrate, each trench defining a semiconductor fin. A local dielectric material is deposited entirely on the semiconductor device and in the trenches to cover each semiconductor fin. The local dielectric material disposed in each trench is recessed a predetermined distance below the semiconductor fins. An etch resistant layer, which is resistant to at least one of a gate etching process and a spacer etching process, is formed on an upper surface of each recessed local dielectric material.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Raghavasimhan Sreenivasan
  • Patent number: 8698875
    Abstract: A system and method are presented for estimating the orientation of a panoramic camera mounted on a vehicle relative to the vehicle coordinate frame. An initial pose estimate of the vehicle is determined based on global positioning system data, inertial measurement unit data, and wheel odometry data of the vehicle. Image data from images captured by the camera is processed to obtain one or more tracks, each track including a sequence of matched feature points stemming from a same three-dimensional location. A correction parameter determined from the initial pose estimate and tracks can then be used to correct the orientations of the images captured by the camera. The correction parameter can be optimized by deriving a correction parameter for each of a multitude of distinct subsequences of one or more runs. Statistical analysis can be performed on the determined correction parameters to produce robust estimates.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: April 15, 2014
    Assignee: Google Inc.
    Inventors: Dragomir D. Anguelov, Daniel Filip
  • Patent number: 8698212
    Abstract: Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 15, 2014
    Assignee: Life Technologies Corporation
    Inventor: Mark Milgrew
  • Patent number: 8692250
    Abstract: A method for fabricating a TFT array substrate including the following steps is provided. A substrate having a pixel region and a photosensitive region is provided. A first patterned conductive layer is formed on the substrate, wherein the first patterned conductive layer includes a gate electrode disposed in the pixel region and a first electrode disposed in the photosensitive region, and a photosensitive dielectric layer is formed on the first electrode. A gate insulation layer is formed to cover the gate electrode, the photosensitive dielectric layer and the first electrode. A patterned semiconductor layer is formed on the gate insulation layer above the gate electrode. A source electrode and a drain electrode are formed on the patterned semiconductor layer at two sides of the gate electrode, wherein the gate electrode, the source electrode, and the drain electrode constitute a TFT. A second electrode is formed on the photosensitive dielectric layer.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: April 8, 2014
    Assignee: Au Optronics Corporation
    Inventors: Ming-Hsien Lee, Ching-Chieh Shih, An-Thung Cho, Chia-Tien Peng, Kun-Chih Lin
  • Patent number: 8687126
    Abstract: Provided is a digital image signal processing method, a recording medium for recording the method, and a digital image signal processing apparatus, in which a storage area of a memory may be efficiently used and an image desired by a user can be stored even when the storage area of the memory is insufficient. According to the present invention, a scene of an image may be recognized and a resolution and an image quality may be modified according to the recognized scene, thereby efficiently using the storage area of the memory.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jang-won Lee
  • Patent number: 8685834
    Abstract: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Haw Tsao, Chender Huang, Chuen-Jye Lin
  • Patent number: 8686442
    Abstract: The present invention provides a nitride semiconductor light emitting device having an n-electrode that has an Au face excellent in ohmic contacts to an n-type nitride semiconductor and excellent in mounting properties, and a method of manufacturing the same. The nitride semiconductor light emitting device uses an n-electrode having a three-layer laminate structure that is composed of a first layer containing aluminum nitride and having a thickness not less than 1 nm or less than 5 nm, a second layer containing one or more metals selected from Ti, Zr, Hf, Mo, and Pt, and a third layer made of Au, from the near side of the n-type nitride semiconductor in order of mention. The n-electrode thus formed is then annealed to obtain ohmic contacts to the n-type nitride semiconductor.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: April 1, 2014
    Assignee: Oclaro Japan, Inc.
    Inventors: Akihisa Terano, Aki Takei
  • Patent number: 8686412
    Abstract: A microelectronic device includes a thin film transistor having an oxide semiconductor channel and an organic polymer passivation layer formed on the oxide semiconductor channel.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: April 1, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Gregory Herman, Benjamin Clark, Zhizhang Chen