Abstract: Resistive memory cells having a plurality of heaters and methods of operating and forming the same are described herein. As an example, a resistive memory cell may include a resistance variable material located between a first electrode and a second electrode, a first heater coupled to a first portion of the resistance variable material, a second heater coupled to a second portion of the resistance variable material, a third heater coupled to a third portion of resistance variable material, and a conductive material coupled to the first, second, and third heaters.

Abstract: Semiconductor structures and methods of manufacture semiconductors are provided which relate to heterojunction bipolar transistors. The method includes forming two devices connected by metal wires on a same wiring level. The metal wire of a first of the two devices is formed by selectively forming a metal cap layer on copper wiring structures.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air.

Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.

Abstract: An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit, a second circuit, at least one interconnect line and an electrostatic discharge protection circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically connected to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically connected to the second circuit. The first internal bonding pad is electrically connected to the second internal bonding pad via the bonding wire. The first internal bonding pad is electrically connected to the electrostatic discharge protection circuit via the interconnect line. The electrostatic discharge protection circuit is electrically connected to the external bonding pad which is used for electrically connecting an external package lead.

Abstract: The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization. The processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes.

Abstract: Improved semiconductor substrates are provided that employ a wide bandgap material between the channel and the insulator. A semiconductor substrate comprises a channel layer comprised of a III-V material; an insulator layer; and a wide bandgap material between the channel layer and the insulator layer, wherein a conduction band offset (?Ec) between the channel layer and the wide bandgap material is between 0.05 eV and 0.8 eV. The channel layer can be comprised of, for example, In1-xGaxAs or In1-xGaxSb, with x varying from 0 to 1. The wide bandgap material can be comprised of, for example, In1-yAlyAs, In1-yAlyP, Al1-yGayAs or In1-yGayP, with y varying from 0 to 1.

Abstract: A CMOS imaging device formed of plural CMOS photosensors arranged in a row and column formation, wherein a first CMOS photosensor and a second CMOS photosensor adjacent with each other in a column direction are formed in a single, continuous device region defined on a semiconductor substrate by a device isolation region.

Abstract: To provide a simple method for manufacturing a semiconductor device in which deterioration in characteristics due to electrostatic discharge is reduced, a plurality of element layers each having a semiconductor integrated circuit and an antenna are sealed between a first insulator and a second insulator; a layered structure having a first conductive layer formed on a surface of the first insulator, the first insulator, the element layers, the second insulator, and a second conductive layer formed on a surface of the second insulator is formed; and the first insulator and the second insulator are melted, whereby the layered structure is divided so as to include at least one of the semiconductor integrated circuits and one of the antennas.

Abstract: A method for intensifying identification of three-dimensional objects identification includes utilizing a left eye camera and a right eye camera to capture a left eye image and a right eye image, calibrating the left eye image and the right eye image to generate a calibrated left eye image and a calibrated right eye image, using the calibrated left eye image and the calibrated right eye image to generate a disparity map, differentiating a three-dimensional object from a background image according to the disparity map, projecting the three-dimensional object onto a plan view, filtering noise out of the plan view to generate a filtered three-dimensional object, determining whether the filtered three-dimensional object contains at least two three-dimensional objects, and separating the at least two three-dimensional objects if the filtered three-dimensional object contains at least two three-dimensional objects.

Abstract: A first semiconductor device comprising: a first conductivity type drift region formed in a semiconductor substrate; a second conductivity type body region formed at an upper surface of the semiconductor substrate on an upper surface side of the drift region; a first conductivity type first semiconductor region formed on a part of an upper surface of the body region; and a trench gate type insulated gate penetrating the first semiconductor region and the body region, and formed to a depth at which the insulated gate contacts the drift region. A part of the insulated gate on a drift region side relative to the body region is deeper at a center portion than at both end portions in a longitudinal direction of the insulated gate.

Abstract: A condenser microphone having a flexure hinge diaphragm and a method of manufacturing the same are provided. The method includes the steps of: forming a lower silicon layer and a first insulating layer; forming an upper silicon layer on the first insulating layer; forming sound holes by patterning the upper silicon layer; forming a second insulating layer and a conductive layer on the upper silicon layer; forming a passivation layer on the conductive layer; forming a sacrificial layer on the passivation layer; depositing a diaphragm on the sacrificial layer, and forming air holes passing through the diaphragm; forming electrode pads on the passivation layer and a region of the diaphragm; and etching the layers to form an air gap between the diaphragm and the upper silicon layer. Consequently, a manufacturing process may improve the sensitivity and reduce the size of the condenser microphone.

Abstract: An object is to provide a method for manufacturing a light-emitting device including a flexible substrate, in which separation is performed without separation at the interface between the light-emitting layer and the electrode. A spacer formed of a light absorbing material which absorbs laser light is formed over a partition of one of substrates, a coloring layer is formed over the other substrate, and the substrates are bonded to each other with the use of a bonding layer. The light-emitting layer and the electrode which are formed over the spacer are irradiated with laser light through the coloring layer, so that at least the bonding layer among the light-emitting layer, the electrode, the coloring layer, and the bonding layer is melted to form a fixed portion where the bonding layer and the spacer are bonded by welding.

Abstract: Provided are three-dimensional semiconductor devices. The device includes conductive patterns stacked on a substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern includes a first doped region disposed adjacent to at least one of the conductive patterns, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract: At least part of a semiconductor layer or a semiconductor substrate includes a semiconductor region having a large energy gap. The semiconductor region having a large energy gap is preferably formed from silicon carbide and is provided in a position at least overlapping with a gate electrode provided with an insulating layer between the semiconductor region and the gate electrode. By making a structure in which the semiconductor region is included in a channel formation region, a dielectric breakdown voltage is improved.

Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.

Abstract: A semiconductor device includes a semiconductor element, a wiring board including a conductor portion formed on a first surface thereof on which the semiconductor element is mounted, the conductor portion being electrically connected to the semiconductor element, and a concave cap provided to seal the first surface of the wiring board, the concave cap being mounted through an adhesive on the first surface of the wiring board In the semiconductor device, a sidewall portion of the concave cap includes an inside surface facing toward the conductor portion of the wiring board, an outside surface positioned on an opposite side to the inside surface, and a bottom surface adhered onto the first surface of the wiring board. The sidewall portion of the concave cap is provided so that a thickness thereof becomes thinner at a portion extending from the outside surface to the bottom surface.

Abstract: In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.

Abstract: A phosphor blend for an LED light source is provided wherein the phosphor blend comprises from about 7 to about 12 weight percent of a cerium-activated yttrium aluminum garnet phosphor, from about 3 to about 6 weight percent of a europium-activated strontium calcium silicon nitride phosphor, from about 15 to about 20 weight percent of a europium-activated calcium silicon nitride phosphor, and from about 55 to about 80 weight percent of a europium-activated calcium magnesium chlorosilicate phosphor. An LED light source in accordance with this invention has a B:G:R ratio for a 3200K tungsten balanced color film of X:Y:Z when directly exposed through a nominal photographic lens, wherein X, Y and Z each have a value from 0.90 to 1.10.

Abstract: An SRAM structure and method which includes a semiconductor on insulator (SOI) substrate which includes a semiconductor substrate, an insulating layer and a semiconductor on insulator (SOI) layer. The SOI layer has a first thickness. The SRAM structure further includes a FinFET transistor formed on the SOI substrate including a first defined portion of the SOI layer of the first thickness forming an active layer of the FinFET transistor and a gate dielectric on the first defined portion of the SOI layer and a planar transistor formed on the SOI substrate including a second defined portion of the SOI layer of a second thickness forming an active layer of the planar transistor and a gate dielectric on the second defined portion of the SOI layer. The first thickness is greater than the second thickness. Also included is a gate electrode on the FinFET transistor and the planar transistor.