Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2?x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract: A microphone includes a first diaphragm and a second diaphragm coupled to the first diaphragm by a closed air volume. The first diaphragm and the second diaphragm each constitutes a piezoelectric diaphragm. The first diaphragm and the second diaphragm are electrically coupled so that movement of the first diaphragm causes movement of the second diaphragm.

Abstract: A method of manufacturing an ohmic contact layer and a method of manufacturing a top emission type nitride-based light emitting device having the ohmic contact layer are provided. The method of manufacturing an ohmic contact layer includes: forming a first conductive material layer on a semiconductor layer; forming a mask layer having a plurality of nano-sized islands on the first conductive material layer; forming a second conductive material layer on the first conductive material layer and the mask layer; and removing the portion of the second conductive material on the islands and the islands through a lift-off process using a solvent. The method ensures the maintenance of good electrical characteristics and an increase of the light extraction efficiency.

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract: A method for fabricating a dynamic random access memory (DRAM) capacitor includes forming a first electrode layer, forming a catalytic layer on the first electrode layer, optionally annealing the catalytic layer, forming a dielectric layer on the catalytic layer, optionally annealing the dielectric layer, forming a second electrode layer on the dielectric layer, and optionally annealing the capacitor stack. Advantageously, the electrode layers are TiN, the catalytic layer is MoO2?x where x is between 0 and 2, and the physical thickness of the catalytic layer is between about 0.5 nm and about 10 nm, and the dielectric layer is ZrO2.

Abstract: A package structure is adapted for mounting at least one light emitting diode (LED) die. The package structure includes an insulating housing, and a lead frame unit including two spaced-apart conductive bodies. Each of the conductive bodies has opposite first and second conductive terminals spaced-apart from each other along an axial direction. The first conductive terminals extend into the insulating housing. The second conductive terminals are exposed outwardly of the insulating housing. Each of the conductive bodies further has two side edges spaced-apart from each other along a transverse direction perpendicular to the axial direction, and a concave-convex structure disposed at the side edges and surrounded by the insulating housing.

Abstract: An organic light-emitting device includes an anode, a cathode, and an organic compound layer interposed between the anode and the cathode. The organic compound layer contains a heterocyclic compound having 4,10-Diazachrysene.

Abstract: A semiconductor integrated circuit includes a semiconductor chip, a plurality of first through-chip vias formed vertically through the semiconductor chip and configured to operate as an interface for a first power supply, and a first common conductive layer provided over the semiconductor chip and coupling the plurality of first through-chip vias to each other in a horizontal direction.

Abstract: The present disclosure relates to a method for fast and precise alignment and mounting of a top die onto an interposer wafer. The method is performed by applying a hydrophobic self assembled monolayer to a carrier wafer in a pattern defining a top die placement region correlating to an arrangement of a top die on an interposer wafer. A liquid is provided into the top die placement region and a top die is placed into contact with the liquid. The surface tension of the liquid automatically aligns the top die by generating a force causing the top die to overlap with the top die placement region. The liquid is then eliminated and the top die is affixed to the carrier wafer. The carrier wafer is bonded to the interposer wafer, bringing the top die into contact with an interposer.

Abstract: It is made possible to restrain generation of defects at the time of insulating film formation. A method for manufacturing a semiconductor device, includes: placing a semiconductor substrate into an atmosphere, thereby forming a nitride film on a surface of the semiconductor substrate, the atmosphere containing a first nitriding gas nitriding the surface of the semiconductor substrate and a first diluent gas not actually reacting with the semiconductor substrate, the ratio of the sum of the partial pressure of the first diluent gas and the partial pressure of the first nitriding gas to the partial pressure of the first nitriding gas being 5 or higher, and the total pressure of the atmosphere being 40 Torr or lower.

Abstract: A switching element of the present invention utilizes electro-chemical reactions to operate, and comprises ion conductive layer 54 capable of conducting metal ions, first electrode 49 arranged in contact with the ion conductive layer, and second electrode 58 for supplying metal ions to the ion conductive layer, wherein an oxygen absorption layer 55 which contains a material more prone to oxidization than the second electrode is formed in contact with the second electrode.

Abstract: A novel interconnection structure which is excellent in adhesion and is capable of realizing low resistance and low contact resistance is provided. An interconnection structure including an interconnection film and a semiconductor layer of a thin film transistor above a substrate in this order from the side of a substrate, wherein the semiconductor layer is composed of an oxide semiconductor, is provided.

Abstract: An induction hob having a plurality of induction heating elements; a control unit to operate the plurality of induction heating elements so as to heat at least one flexibly definable heating zone in a synchronized manner; and a measurement array to measure a heating power generated by the plurality of induction heating elements. The measurement array measures a sum of heating powers of at least two induction heating elements and the control unit uses the sum of heating powers to regulate the heating power generated by the plurality of induction heating elements.

Abstract: A method of manufacturing a semiconductor device, in which an amorphous silicon layer is formed into a shape of a gate electrode of a MOS transistor, and then impurity is implanted to a surface of a silicon substrate from a diagonal direction using the amorphous silicon layer as a mask.

Abstract: In an exemplary embodiment, a method takes as an input a package substrate on which multiple capacitors have been mounted in a ring as part of a design to effectuate on-package decoupling. The method involves plasma cleaning the package substrate and the capacitors to remove organic contaminants. The method then involves applying a thermoset plastic to encase the capacitors on the package substrate. In one embodiment, a heated metal mold is utilized and the thermoset plastic is placed therein. The method includes opening the metal mold and curing the molded thermoset plastic by baking the molded thermoset plastic at an elevated temperature.

Abstract: High power wide band-gap MOSFET-gated bipolar junction transistors (“MGT”) are provided that include a first wide band-gap bipolar junction transistor (“BJT”) having a first collector, a first emitter and a first base, a wide band-gap MOSFET having a source region that is configured to provide a current to the base of the first wide band-gap BJT and a second wide band-gap BJT having a second collector that is electrically connected to the first collector, a second emitter that is electrically connected to the first emitter, and a second base that is electrically connected to the first base.

Abstract: The present invention relates to a solar power generation device which includes an electric double-layer capacitor and a solar cell. The electric double-layer capacitor includes a pair of current collectors formed using a light-transmitting conductive material; active materials which are dispersed on the pair of current collectors; a light-transmitting electrolyte layer which is provided between the pair of current collectors; and a terminal portion which is electrically connected to the current collector. The solar cell includes, over a light-transmitting substrate, a first light-transmitting conductive film; a photoelectric conversion layer which is provided in contact with the first light-transmitting conductive film; and a second light-transmitting conductive film which is provided in contact with the photoelectric conversion layer.

Abstract: An integrated circuit device (e.g., a logic device or a memory device) having (i) a memory cell array which includes a plurality of memory cells (for example, memory cells having electrically floating body transistors) arranged in a matrix of rows and columns, wherein each memory cell includes at least one transistor having a gate, gate dielectric and first, second and body regions, wherein: (i) the body region of each transistor is electrically floating and (ii) the transistors of adjacent memory cells include a layout that provides a common first region and/or a common second region. Each common first region and/or second regions of transistors of adjacent memory cells includes a barrier disposed therein and/or therebetween, wherein each barrier provides a discontinuity in the common regions and/or includes one or more electrical characteristics that are different from one or more corresponding electrical characteristics of the common regions.

Abstract: A method of manufacturing a non-volatile memory device, can be provided by forming a gate insulating layer and a gate conductive layer on a substrate that includes active regions that are defined by device isolation regions that include a carbon-containing silicon oxide layer. The gate conductive layer and the gate insulating layer can be sequentially etched to expose the carbon-containing silicon oxide layer. The carbon-containing silicon oxide layer can be wet-etched to recess a surface of the carbon-containing silicon oxide layer to below a surface of the substrate. Then, an interlayer insulating layer can be formed between the gate insulating layer and the gate conductive layer on the carbon-containing silicon oxide layer, where an air gap can be formed between the carbon-containing silicon oxide layer and the gate insulating layer.