Abstract: A system and method for incremental redundancy transmission in a communication system. A time slot is provided having at least one sub-slot with a fixed size, and a data block sized to fit in the sub-slot, a header having a one data block sequence number in the header for the time slot. A parity block is sized smaller than the data block such that the parity block and the data block sequence number fit within the sub-slot. The data block and parity block are transmitted in the sub-slot within the time slot. In the header for the time slot the number of data blocks and parity blocks transmitted are identified.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: A label switching type packet forwarding apparatus having a routing information table in which a forwarding type of a reception packet, output port identification information, and output routing information of a specific layer in the OSI reference model determined by the forwarding type are defined in correspondence with routing information which is found upon reception of a packet, for converting a header of a reception packet in accordance with the packet forwarding type and the output routing information obtained by a table search.

Abstract: Connection ports for interconnecting functional modules in an integrated circuit are described. The connection ports provide enhanced functionality based around a common port primitive. This simplifies port design and selection and also allows a common packet protocol to be used for communication of packets across the packet router. In particular, there is improved functionality of target ports which allow out of order requests to be dealt with and out of order responses to be generated.

Abstract: An apparatus for receiving and/or transmitting signals using orthogonal frequency division multiplexing, said apparatus being adapted for outputting a first output signal, comprising: a time synchronisation circuit, being adapted for determination of control information from a first signal, said first signal comprising at least of a first part being a non-orthogonal frequency division multiplexing signal and a second part being an orthogonal frequency division multiplexing signal, said determination of control information exploiting said first part of said first signal; said time synchronisation circuit, further being adapted for converting said second part of said first signal into a second signal, being in time domain representation; a transformation circuit at least converting said second signal into a third signal, being in frequency domain representation; a first frequency domain circuit, at least converting said third signal into said first output signal; and said second signal and said second part

Abstract: A method and apparatus for frame synchronization in a display circuit is achieved by first measuring a difference between a first frame period and a second frame period. When the difference exceeds a threshold, the first frame period is adjusted by replacing the clock corresponding to the first frame period with one of a slow frame rate and a fast frame rate. The slow and fast frame rates closely approximate an ideal frame rate that would synchronize the two frame periods. By switching between the slow and fast frame rates, the average frame rate approaches the ideal frame rate over time, and the two frame periods are effectively synchronized.

Abstract: A method for transferring a data packet from a compressor to a decompressor said data packet including a header with header data fields. A number of the header data fields that remain constant during the data transfer are stored in the decompressor. In a compressed data packet, a header data field that varies is replaced by a compressed value identifying a data packet in a compression sequence. In the decompressor context data comprising information for relating the received compressed value to a corresponding compression sequence is maintained and the information is updated according to the received compressed values. The compressed value and the information of the corresponding compression sequence are used for mapping the compressed value into a decompressed header data field. Thus compressed data is unambiguously mapped to a full packet data header field in the decompressor side throughout the session.

Abstract: A process controller that is communicatively coupled to an external field device via a communication network uses a shadow function block disposed within a process controller to enable implementation of a control routine that uses both an internal function block disposed within the process controller and an external function block disposed within the external field device. The shadow function block includes a communication port that communicates with the external function block via the communication network to thereby receive data pertaining to the external function block, a memory that stores the received data according to a configuration protocol of the internal function block and an output that provides the stored external function block data to the internal function block according to the configuration protocol of the internal function block.

Abstract: A pipelined linecard architecture for receiving, modifying, switching, buffering, queuing and dequeuing packets for transmission in a communications network. The linecard has two paths: the receive path, which carries packets into the switch device from the network, and the transmit path, which carries packets from the switch to the network. In the receive path, received packets are processed and switched in an asynchronous, multi-stage pipeline utilizing programmable data structures for fast table lookup and linked list traversal. The pipelined switch operates on several packets in parallel while determining each packet's routing destination. Once that determination is made, each packet is modified to contain new routing information as well as additional header data to help speed it through the switch. Each packet is then buffered and enqueued for transmission over the switching fabric to the linecard attached to the proper destination port.

Abstract: A method and apparatus for implementing multicast in a space-based communication system is disclosed. The present invention allows for the use of a buffer in which to store data packets prior to replication in a multicast application. The present apparatus includes a buffer (102), a header memory (103), and an ASIC (101) to store and extract received data packets and replicate them as required. The ASIC (101) includes a switch interface (201), a queue manager (203), a header processor (205), a holding buffer (207), and a arbitration interface (209). The switch interface (201) is connected to the queue manager (203). The queue manager (203) is connected to the buffer (102), the header processor 205, the holding buffer (207), and the arbitration and switch interface (204). The header processor (205) is connected to the header memory (103).

Abstract: A scalable multicast protocol buffers the multicast messages at a subset of “C” members, where C is selected to reduce to an acceptable level the probability that a given message will be lost before it reaches at least one of the C members. When a member receives a multicast message, the member determines whether or not it should buffer the message by manipulating a string of bytes that is unique to both the message and the member and determining if the result is less than a calculated value C/n, where “n” is the number of known members. When one of the C bufferers thereafter receives a gossip message that indicates that the multicast message has been lost to the gossiping member, the bufferer retransmits the message to the gossiping member. When a member that is not one of the C bufferers receives such a gossip message, the member determines which members are bufferers of the lost message and requests that one of the bufferers retransmit the message to the gossiping member.

Abstract: Methods and apparatus for allowing a packet data connection to be established by sending an indication of a network address through a telephony path. In a first embodiment, a protocol stack initiates the establisment of an Internet connection by sending a data segment through a public switched telephone network (PSTN) telephony path and then operates and maintains the Internet connection on separate packet connection. Dialing digits are used to indicate the address of a remote computer or wireless device via the telephony path. This invention also enables mixed PSTN/internet multimedia telephone calls. In an exemplary embodiment, when a point-to-point telephone PSTN connection is established, a screen of information automatically appears at one or both ends of the connection via the Internet.

Abstract: Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

Abstract: A pipelined arbitration mechanism allows a routing control decision to be effected for a later packet while a current packet is being transferred. The later packet can be issued a fixed number of cycles after the current request. The mechanism has particular advantages when used with a plurality of functional modules connected to a packet router, whereby a single functional module can generate a current request relating to a current packet and a deferred arbitration request relating to a later packet to be issued a fixed number of cycles after the current request.

Abstract: According to the method of the invention, connections are divided into at least two different connection classes according to their requirements for transmission delay. The control system of the base station subsystem maintains a record of the transmission needs of the users logged in different categories and based thereon divides the available radio resources into slots of suitable capacity. For connections with stringent requirements for transmission delay, circuit-switched connections are allocated with a bandwidth which can be controlled dynamically. Then from the resource pool still unassigned after the resource allocation to the circuit-switched connections, a sufficient amount of resources are allocated on a time-limited basis allocation for each allocation period to connections having a higher tolerance for delay so as to accomplish transmission, e.g. of a given amount of data.

Abstract: A lateral semiconductor element (10) in thin-film SOI technology comprises an insulator layer (14) which rests on a substrate (12) and is buried under a thin silicon film (16), on top of which the source, or anode, contact (18) and the drain, or cathode, contact (22) are mounted. The anode contact (18) and the cathode contact (22) each lie over separate shield regions (28,30) within substrate (12), with the anode contact (18) being electrically connected with substrate (12).

Abstract: In order to eliminate the disconnection of a pixel electrode caused by a change in shape of an interlayer insulating film at the ends of metal wiring, a resin film is formed at the ends of the metal wiring. Because of the resin film at the ends of the metal wiring, the step difference of the ends of the metal wiring is alleviated, and even if the interlayer insulating film is changed in shape, the ends of the metal wiring is prevented from peeling, whereby the disconnection of the pixel electrode can be prevented. Furthermore, the resin film flattens the surface of the interlayer insulating film, and prevents an alignment defect of liquid crystal molecules and a non-uniform electric field, thereby suppressing a minute defect of a light-emitting device caused by the roughness of the surface of the pixel electrode.

Abstract: The invention relates to a semiconductor memory (1) having a plurality of memory-cell arrays (2), a plurality of sense-amplifier areas (3) and a plurality of driver areas (4) on a semiconductor substrate (7) of a first conductivity type, each of the multiple sense-amplifier areas (3) and multiple driver areas (4) containing at least one first well (9) of the first conductivity type and/or at least one second well (10) of a second conductivity type, and each first well (9) of the driver areas (4) being isolated from the semiconductor substrate (7) by a buried horizontal layer (8) of the second conductivity type.

Abstract: A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250° C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Abstract: A silicon oxide film (1701) serving as a gate insulating film of a semiconductor device contains Kr. Therefore, the stress in the silicon oxide film (1701) and the stress at the interface between silicon and the silicon oxide film are relaxed, and the silicon oxide film has a high quality even though it was formed at a low temperature. The uniformity of thickness of the silicon oxide film (1701) on the silicon of the side wall of a groove (recess) in the element isolating region is 30% or less. Consequently, the silicon oxide film (1701) has its characteristics and reliability superior to those of a silicon thermal oxide film, and the element isolating region can be made small, thereby realizing a high-performance transistor integrated circuit preferably adaptable to an SOI transistor and a TFT.