Abstract: A semiconductor device having trap sites passivated with deuterium has enhanced immunity to hot carrier effects. The trap sites which are passivated with deuterium are encapsulated beneath a barrier film and are therefore resistant to having the deuterium diffuse away from the trap sites during subsequent high temperature processing operations.

Abstract: To provide an electronic device capable of bright image display. A pixel is structured such that a switching TFT and a current controlling TFT are formed on a substrate and an EL element is electrically connected to the current controlling TFT. A gate capacitor formed between a gate electrode of the current controlling TFT and an LDD region thereof holds a voltage applied to the gate electrode, and hence a capacitor (condenser) is not particularly necessary in the pixel, thereby making the effective light emission area of the pixel large.

Abstract: A novel structure of nonvolatile memory is formed on p type silicon and includes a stacked gate, a tunneling dielectric layer, a floating gate (FG), a dielectric layer and a control gate (CG). One side of the stacked gate has a source region and the other has a drain region, wherein the surface of the source region includes a thin metal silicide connected with a channel region to form a Schottky barrier. A tilted angle implant with As or P doping is performed on the p type silicon substrate to form a drain region and extend a portion of the drain region to a channel region under the stacked gate. For implanting, an n doped source region is also formed, creating an offset between the source region and the channel region as a result of the tilted angle implant. For programming, the source region is grounded, positive voltage is applied to the drain region and the gate, such that the hot carriers inject into the floating gate through the channel adjacent to the source region.

Abstract: A semiconductor device includes a capacitor formed to have an approximately elliptical cross-sectional shape and extending upwards from upper surface of each said storage node contact. When an arrangement of capacitors is seen vertically from above, rows of capacitors are formed such that, along direction of a major axis of the approximate ellipse, a plurality of capacitors are aligned with regular intervals. When arbitrary one of said capacitor rows is taken as a first capacitor row, a second capacitor row is arranged in parallel therewith, and the capacitors in the first capacitor row and the second capacitor row are aligned out of phase with each other by length corresponding approximately to a sum of width of one transfer gate and width of one space between transfer gates.

Abstract: A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.

Abstract: The inductance element according to the present invention includes: an inductance section, provided above a semiconductor substrate via insulating films, which is composed of a conductive film pattern setted to have a predetermined inductance value; and an impurity region, provided on the semiconductor substrate so as to be positioned at least at an area under the conductive film pattern, which has a grounding potential and a denser impurity than that of the semiconductor substrate. The inductance element is provided in a semiconductor device.

Abstract: A service message system for a switching architecture including at least one Switch Fabric (10, 20) comprising a switch core (15, 25) located in a centralized building and a set of Switch Core Access Layer (SCAL) elements distributed in different physical areas for the attachment to the different Port adapters (30, 31). Each SCAL elements particularly includes a SCAL receive element (11-i) and a SCAL Xmit element (12-i) for the respective access to one input port and one output port via serial links. The service message is based on the use of a Cell qualifier field at the beginning of each cell, which comprises a first and a second field. The first field is the Filtering Control field which permits an easy decoding of a service message cell, when applicable. The second field is used for determining which particular type of service message is conveyed via the cell.

Abstract: A method of operating a network device in a communication system for the transmission of data packets which include network addresses identifying sources and destinations of data, the network device being capable of both bridging and routing decisions and including a forwarding database by means of which a packet including network address data can be forwarded to at least one port and thereby to at least one network path identified by a network address, and packets can be forwarded to at least one port in response to a media access control address. The method comprises establishing a data table which contains entries comprising a network address of an end station to which a packet is destined, a respective media access control address and an identification of at least one port to which the packet will be directed within the device. The table is accessed in response to network addresses and media access control addresses, whereby the same table can be used for both routing and bridging decisions.

Abstract: A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of opposite conductivity type. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers, which are in separated patterns.

Abstract: Apparatus for an electrically programmable and erasable memory device and methods for programming, erasing and reading the device. The device has a single transistor including a source, a drain, a control gate and a floating gate positioned between the control gate, the source and the drain, where the floating gate is capacitively coupled to the drain. At least one part of the floating gate is partly positioned between the control gate, the drain and the source, and the other part of the floating gate overlaps with the drain. Further, the single transistor of the device includes means for injecting hot electrons generated by the drain induced secondary impact ionization onto the floating gate. Additionally, the means are arranged to induce Fowler-Nordheim tunnelling of charges from the floating gate to the drain.

Abstract: Disclosed is a semiconductor device using a gate electrode such as an SRAM, wherein the electrode pattern is a formed with fidelity to a reticle pattern through no complicated layout design. The gate electrode pattern is formed in an area smaller than that of a conventional semiconductor device. In a lithographic step using a reticle pattern provided with substantially linear gate electrode patterns, a projecting portion in which at least a part of a contact region is arranged is formed such that it is included in almost the center of a long side of a linear gate electrode pattern and a concave portion facing at least the entire length of the projecting portion is formed such that it is included in a long side opposite to the projecting portion between transistor regions of a reticle pattern.

Abstract: A nonvolatile memory device has a plurality of nonvolatile memory cells in which a memory gate electrode is formed over a first semiconductor region with a gate insulating film and a gate nitride film interposed therebetween. First and second switch gate electrodes, and first and second signal electrodes used as source/drain electrodes are formed on both sides of the memory gate electrode. Electrons are injected into the gate nitride film from the source side to store information in the memory cells. The memory gate electrode and the switch gate electrodes extend in the same direction. The application of a high electric field to a memory cell which is not selected for writing can be avoided owing to the switch gate electrodes being held in a cut-off state.

Abstract: A semiconductor device comprises a MOS transistor and a resistor. The resistor has a P-type resistor formed from a P-type semiconductor, an N-type resistor formed from an N-type semiconductor and disposed adjacent the P-type resistor, and an insulating film disposed between the P-type and N-type resistors. The P-type resistor is arranged at the low potential side of the semiconductor device and the N-type resistor is arranged at the high potential side thereof. A portion of the insulating film between the P-type and N-type resistors is made electrically conductive by irradiating the portion with a laser beam to destroy the insulating property thereof to thereby achieve conductivity between the P-type and N-type resistors. A gate electrode of the MOS transistor is formed of a P-type polysilicon thin film having the same high concentration impurity as that of the region where the P-type resistor is in contact with a metal wiring, thereby enhancing the current driving capacity of a driver MOS.

Abstract: In a semiconductor chip, conductive tracks run in a rewiring layer from contact pads to contact elevations. The contact pads are formed as vias. The conductive tracks are constructed in sections as bottom electrodes of trimming capacitors. The top electrode of the trimming capacitors is formed by a metal plane of the rewiring layer.

Abstract: The invention provides a nonvolatile semiconductor device, or the like. According to the fabrication process of the present invention, silica glass containing boron or phosphorous is used as a material of high absorbency, which is treated in the vapor phase HF atmosphere and, therefore, selective etching of silica glass, only, of high absorbency becomes possible so that a void area can be formed beneath the fin of the floating gate. Accordingly, the absolute value of the parasitic capacitance between the floating gate and the substrate is decreased. In addition, the degree of the fluctuation of the parasitic capacitance due to the manufacturing process can be restricted to a low level. Accordingly, a nonvolatile semiconductor device of high performance can be gained without lowering the yield.

Abstract: A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized seminconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.

Abstract: A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.

Abstract: An antenna structure is fabricated on a chip. The antenna structure includes a shielding layer, a dielectric layer and an antenna layer. The shielding layer includes a plurality of mutually isolated regions. The entire structure may be fabricated using conventional CMOS processes.

Abstract: A semiconductor memory device comprises a first transistor including a source region, a drain region, a first channel region of a semiconductor material formed on an insulating film and connecting the source region and the drain region, and a gate electrode for controlling potential of the first channel region; a second transistor including a source region, a drain region, a second channel region of a semiconductor material connecting the source region and the drain region, a second gate electrode for controlling potential of the second channel region, and a charge storage region coupled with the second channel region by electrostatic capacity; wherein the source region of the second transistor is connected to a source line, one end of the source or the drain region of the first transistor is connected to the charge storage region of the second transistor, the other end of the source or the drain region of the first transistor is connected to a data line.

Abstract: A flat panel display device with improved electrical characteristics and a simplified manufacturing process is disclosed. The device includes a semiconductor layer formed on an insulating substrate; source and drain electrodes directly contacting both end portions of the semiconductor layer, respectively; a pixel electrode having an opening portion formed thereon; a first insulating layer formed over the remaining portion of the insulating substrate except for the opening portion; a gate electrode formed on a portion of the first insulating layer over the semiconductor layer; and source and drain regions formed in both end portions of the semiconductor layer.