Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

Abstract: In vertically stacked device structures, a buried interconnect and bottom contacts can be formed, thereby allowing connections to be made to device terminals from both below and above the stacked device structures. Techniques herein include a structure that enables electrical access to each independent device terminal of multiple devices, stacked on top of each other, without interfering with other devices and the local connections that are needed.

Abstract: The present invention relates to a light emitting layer material comprising: a polycyclic aromatic compound (1) in which a plurality of aromatic rings are linked by a boron atom and a oxygen atom or a nitrogen atom; and a specific anthracene-based compound (3) that achieves optimum light-emission characteristics in combination with said polycyclic aromatic compound. With this light emitting layer material having optimum light emitting characteristics, it is possible to provide an excellent organic EL element. Ring A to ring C are an aryl ring or the like, Y1 is B (boron), X1 and X2 are —O— or >N—R (provided that at least one is —O—), X is a group represented by formula (3-X1), (3-X2), or (3-X3), Y is —O—, —S— or >N—R29, R29 is a hydrogen atom or an optionally substituted aryl, Ar1 to Ar4 are phenyl, a group represented by formula (4), or the like, and both Ar1 and Ar3 do not simultaneously represent a phenyl.

Abstract: A liquid molding compound for protecting five edges of a semiconductor chip and a preparation method thereof are disclosed. The liquid molding compound includes 15 to 40 parts by mass of an epoxy resin, 15 to 35 parts by mass of a curing agent, 0.1 to 3 parts by mass of a curing accelerator, 4 to 15 parts by mass of a toughening agent, 75 to 150 parts by mass of an inorganic filler, and 0.1 to 5 parts by mass of a coupling agent. The epoxy resin is one or more selected from the group consisting of a bisphenol A epoxy resin, a bisphenol F epoxy resin, and a biphenyl epoxy resin. The toughening agent is an adduct of an epoxy resin and a carboxyl-terminated liquid butyronitrile rubber, and the curing agent is a phenol-formaldehyde resin. The molding compound has a low coefficient of thermal expansion (CTE).

Abstract: The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.

Abstract: The organic electric element comprising a compound represented by Formula 1 as material of an emission-auxiliary layer and an electronic device thereof are disclosed, and by comprising the compound represented by Formula 1 in an emission-auxiliary layer, the driving voltage of the organic electric element can be lowered, and the luminous efficiency and life time of the organic electric element can be improved.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of isolation structures on the semiconductor substrate, and a plurality of blocking structures disposed directly over the isolation structures. The blocking structures have a lower reflectivity than the isolation structures.

Abstract: A semiconductor structure includes an isolation structure disposed in a semiconductor substrate; a gate electrode and a resistor electrode disposed in the semiconductor substrate, wherein the isolation structure is disposed between the gate electrode and the resistor electrode, and the isolation structure is closer to the resistor electrode than the gate electrode. A source/drain (S/D) region is disposed in the semiconductor substrate and between the gate electrode and the isolation structure, wherein the S/D region is electrically connected to the resistor electrode. A conductive structure is disposed in the semiconductor structure and over the isolation structure, wherein the S/D region is electrically connected to the resistor electrode through the conductive structure.

Abstract: A method is performed by a computer for a preprocessing for calculating binding free energy between a first substance and a second substance. The method includes: obtaining a binding structure of the first substance and the second substance under a condition where the second substance is constrained such that a binding state of the second substance to the first substance is maintained in a predetermined state; and then, based on the obtained binding structure, obtaining the binding structure under a condition where the second substance is not constrained.

Abstract: There is provided a method of filling one or more recesses by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, introducing a second reactant to the substrate with a second dose, wherein the first and the second doses overlap in an overlap area where the first and second reactants react and leave an initially substantially unreacted area where the first and the second areas do not overlap; introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant to form deposited material; and etching the deposited material. An apparatus for filling a recess is also disclosed.

Abstract: The present invention relates to a compound of formula (I), wherein R1, R2, R3 and R4 are each independently hydrogen or Ra, with proviso that a pair of two substituents selected from R1 and R2, R2 and R3, and R3 and R4 is linked to one another and forms a group of formula (II); a material for an organic electroluminescence device comprising at least one compound of formula (I); an organic electroluminescence device which comprises an organic thin film layer be-tween an anode and a cathode, wherein the organic thin film layer comprises one or more layers and comprises a light emitting layer, and at least one layer of the organic thin film layer comprises at least one compound of formula (I); and an electronic equipment comprising the inventive organic electroluminescence device.

Abstract: According to the invention there is provided a method of filling one or more gaps created during manufacturing of a feature on a substrate by providing a deposition method comprising; introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant; introducing a second reactant to the substrate with a second dose. The first reactant is introduced with a subsaturating first dose reaching only a top area of the surface of the one or more gaps and the second reactant is introduced with a saturating second dose reaching a bottom area of the surface of the one or more gaps. A third reactant may be provided to the substrate in the reaction chamber with a third dose, the third reactant reacting with at least one of the first and second reactant.

Abstract: A semiconductor device including: a semiconductor substrate; a seed layer that is formed on the semiconductor substrate; and wiring that is formed on the seed layer and includes parallel row portions that are arranged at intervals from each other, and in which penetration passages that penetrate the parallel row portions in a direction in which the parallel rows lined up are formed in the parallel row portions.

Abstract: An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.

Abstract: A transmission circuit includes a first semiconductor device, a second semiconductor device, a first signal line, a second signal line, a third signal line, and a ground line. A differential signal is composed of a first signal and a second signal. The first signal line is configured to connect the first semiconductor device and the second semiconductor device and used to transmit the first signal. The second signal line is configured to connect the first semiconductor device and the second semiconductor device and used to transmit the second signal. The second signal line, the first signal line, the ground line, and the third signal line are disposed in this order. A distance between the first signal line and the ground line is larger than a distance between the first signal line and the second signal line.

Abstract: A circuit board (100) has a first surface (102). A semiconductor chip (200) (first semiconductor chip) is located at the first surface side (102) of the circuit board (100). An insulating layer (300) covers the first surface (102) of the circuit board (100) and the semiconductor chip (200). A conductive path (310) (first conductive path) is electrically connected to the semiconductor chip (200) and extends in the insulating layer (300). A waveguide (320) is optically coupled to the semiconductor chip (200) and extends in the insulating layer (300).

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches in a bulk substrate and methods of manufacture. The structure includes: at least one active device having a channel region of a first semiconductor material; a single air gap under the channel region of the at least one active device; and a second semiconductor material being coplanar with and laterally bounding at least one side of the single air gap, the second semiconductor material being different material than the first semiconductor material.

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first spiral trace layer. The inter-metal dielectric layer has a separating region to divide the second spiral trace layer into line segments. First slit openings each passes through a corresponding line segment, and extends in an extending direction of a length of the corresponding line segment.

Abstract: A display panel and a display device are provided. A pixel electrode of the display panel includes a pixel electrode body and a pixel electrode extension. The pixel electrode body is positioned within the light-emitting section and the pixel electrode extension is positioned within the light-shielding section. When an insulating layer positioned on an overlapping section is perforated, the pixel electrode extension is electrically connected to the signal electrode of other sub-pixel units via a repair line, thereby solving a technical problem that existing display panels possess a limited effect on repairing bright spots.