Abstract: An inverted nanocone structure of the present disclosure includes a first surface, a second surface spaced apart from the first surface by a predetermined distance and having a greater area than the first surface, and a body having an inverted cone shape between the first surface and the second surface, wherein at least one activated point defect center is provided in the body.

Abstract: Aspects of the present disclosure include methods for optimizing pharmacological compound development and methods for optimizing one or more modifications of a compound. Aspects of the present disclosure further include methods for designing treatments for a disease, and methods for designing optimized candidate compounds to treat a disease that causes one or more disease effects. Aspects of the present disclosure further include computer-implemented methods for training a model for pharmacological compound design, and computer-implemented methods for optimizing chemical modification of pharmacological compounds.

Abstract: Various integrated circuits formed using gallium nitride and other materials are described. In one example, an integrated circuit includes a first integrated device formed over a first semiconductor structure in a first region of the integrated circuit, a second integrated device formed over a second semiconductor structure in a second region of the integrated circuit, and a passive component formed over a third region of the integrated circuit, between the first region and the second region. The third region comprises an insulating material, which can be glass in some cases. Further, the passive component can be formed over the glass in the third region. The integrated circuit is designed to avoid electromagnetic coupling between the passive component, during operation of the integrated circuit, and interfacial parasitic conductive layers existing in the first and second semiconductor structures, to improve performance.

Abstract: A semiconductor device structure includes a silicon-on-insulator (SOI) region. The SOI region includes a semiconductor substrate, a buried oxide layer disposed over the semiconductor substrate, and a silicon layer disposed over the buried oxide layer. The semiconductor device structure also includes a first shallow trench isolation (STI) structure penetrating through the silicon layer and the buried oxide layer and extending into the semiconductor substrate. The first STI structure includes a first liner contacting the semiconductor substrate and the silicon layer, a second liner covering the first liner and contacting the buried oxide layer, and a third liner covering the second liner. The first liner, the second liner and the third liner are made of different materials. The first STI structure also includes a first trench filling layer disposed over the third liner and separated from the second liner by the third liner.

Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.

Abstract: Provided are a semiconductor device having small characteristic variations with time and high reliability and an in-vehicle control device using the same, the semiconductor device including a plurality of transistor elements constituting a current mirror circuit or a differential amplifier circuit that requires high relative accuracy.

Abstract: Provided are a wavelength converting particle, a method for manufacturing a wavelength converting particle, and a light-emitting diode containing a wavelength converting particle. The wavelength converting particle comprises a hybrid OIP nanocrystal that converts a wavelength of light generated by an excitation light source into a specified wavelength. Accordingly, it is possible to optically stabilize and improve color purity and light-emission performance without changes in a light-emitting wavelength range.

Abstract: A semiconductor wafer comprises a substrate wafer of monocrystalline silicon and a dopant-containing epitaxial layer of monocrystalline silicon atop the substrate wafer, wherein a non-uniformity of the thickness of the epitaxial layer is not more than 0.5% and a non-uniformity of the specific electrical resistance of the epitaxial layer is not more than 2%.

Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.

Abstract: A method for forming an integrated circuit includes following operations. A substrate having a first region, a second region and an isolation structure is received. A portion of the substrate is removed such that the second region is recessed. A portion of the isolation structure is removed to obtain a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed over the first top surface, the second top surface and the boundary. A dielectric structure is formed over the substrate. A top surface of the first device, a top surface of the second device and a top surface of the dummy structure are aligned with each other.

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

Abstract: A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.

Abstract: A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.

Abstract: A method for automatically generating a universal set of stereoisomers of an organic molecule. The method includes: (1) segmenting an input molecule into a group of fragments; (2) matching the obtained isomer fragments with fragment templates in a fragment template library; (3) generating all isomers of the corresponding fragments according to fragment template information; and (4) traversing all the isomer fragments and sites thereof, and assembling the fragments at the two ends of a broken bond in the step (1) according to all possible sites of a broken-bond atom to obtain all stereoisomers; and if filtering is needed, performing filtering according to a specified filtering rule.

Abstract: The present invention provides a display device, including a display panel and an encapsulation cover disposed on the display panel. Two circles of border sealant are sequentially disposed at intervals between the bonding area of the encapsulation cover and the display panel from periphery to the inside. The invention provides a display device, which adopts a novel encapsulation structure so that it can effectively prevent external water and oxygen from invading into the internal display panel, and therefore improve its own stability.

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.

Abstract: A front-side type image sensor may include a substrate successively including: a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.

Abstract: The present application discloses a method for fabricating a semiconductor device with a pad structure. The method includes providing a substrate, forming a capacitor structure above the substrate, forming a plurality of passivation layers above the capacitor structure, forming a pad opening in the plurality of passivation layers, performing a passivation process comprising soaking the pad opening in a precursor, and forming a pad structure in the pad opening. The precursor is dimethylaminotrimethylsilane or tetramethylsilane. Forming the pad structure in the pad opening comprises forming a pad bottom conductive layer comprising nickel in the pad opening and forming a pad top conductive layer on the pad bottom conductive layer. The pad top conductive layer comprises palladium, cobalt, or a combination thereof.

Abstract: There is provided an aluminum nitride laminate member including: a sapphire substrate having a base surface on which bumps are distributed periodically, each bump having a height of smaller than or equal to 500 nm; and an aluminum nitride layer provided on the base surface and having a surface on which protrusions are formed above the apices of the bumps.