Abstract: A rotary encoder apparatus of an incremental-type construction, including: a rotary unit mechanically joined to a movable machine; a unit for outputting at least two signals having a phase shift and a periodic waveform in response to rotation of the rotary unit; a battery-type power supply; and an electric circuit including a circuit for generating a timing pulse having predetermined frequency and pulse width, a circuit for detecting a change of the signals from the signal outputting circuit and for outputting a pulse signal in response to the change of signals, and a circuit for counting the pulse signal from the signal-change detecting circuit. The apparatus may be optical or magnetic in construction.
Abstract: A differential pulse code modulation coder has a pair of series connected arithmetic units connected to the input of a quantizer, with the output of the quantizer connected through a first multiplier to an input of the second arithmetic unit, and the output of the quantizer connected through an adder and further multiplier to the second input of the first arithmetic unit, the second input of said adder being derived from the output of said second multiplier, whereby greater internal calculation speed is realized.
Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I.sup.2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.
Abstract: A utility meter has a plurality of rotating shafts which have angular positions corresponding to the digits of a consumption reading. A cam is attached to that shaft which is associated with the least significant digit. The cam has a light reflecting track. Light from a light source is reflected off the track to a photodetector along an optical path which varies in length in accordance with angular cam position. Electronic circuitry is connected to the light source and photodetector and produces an output signal in digital form which has a frequency related to intensity of light incident upon the photodetector.
September 29, 1981
Date of Patent:
February 19, 1985
David A. Krohn, Louis A. Buffone, Edmond I. Vinarub
Abstract: A signal processor which involves separation of the cell signals from a magnetic resonance gyro (MRG) using phase locked loops that also serve as frequency multipliers, phase shifting one cell output to maintain phase comparisons within the monotonic region of the phase detectors, PDM/Digital conversion of the MRG signals and finally microcomputer processing to obtain gyro angle to the required resolution and update rate.
Abstract: A display circuit for displaying analog input voltages in a digital fashion using a parallel comparison type analog-digital converter includes a voltage generator for generating a plurality of reference voltages quantized at a predetermined voltage width, a plurality of comparators corresponding to the plurality of reference voltages for comparing the reference voltages and an analog input voltage as input, and display means for encoding and displaying the output of the plurality of comparators, is provided with modulating apparatus for modulating one of the inputs of each of the plurality of comparators periodically within the range of the predetermined voltage width.
Abstract: A digital-to-analog converter for use in a television tuning system to convert bits stored in a register to a corresponding tuning voltage includes a counter for generating binary pulse signals having pulses with durations proportional to powers of 2 and a plurality of selection gates for selecting ones of the binary pulse signals in accordance with the states of respective bits stored in the register to generate a plurality of output pulse signals each having G pulses with durations proportional to ##EQU1## where n is the number of the respective bit. The output pulse signals are justified with respect to each other by position-determining gates and combined to form G clusters of contiguous but non-overlapping pulses. The resulting pulse signal is filtered by a low/pass filter to derive the tuning voltage. G is selected as a compromise value consistent with both reasonable temperature stability and a reasonably fast filter response.
Abstract: A method of recording data, such as trade marks, for searching by data processing means comprising recording the data on data processing supports first as it normally appears and again according to an alphabet code, phonic code or cryptographic code, filing the data processing supports in a logical order by the alphabet code and preparing lists of the data.
Abstract: An analog current I.sub.1, to be digitized is fed continuously to the input of an integrator. Two pulse counters, serially connected, algebraically count pulses from a pulse generator, the first pulse counter of the two setting, upon overflow, a bistable element to one of its states. The bistable element will remain in the state until the first pulse of the pulse generator, after the next change-over of the threshold switch occurs. In accordance with the state of the threshold switch, the bistable flip-flop circuit permits either a current I.sub.2, or a current I.sub.3 (the two currents being of opposite polarity) to be applied, simultaneously with the current I.sub.1, to the integrator by suitable switches during predetermined time intervals W. The time interval W is defined as the sum of the timing intervals occurring between two successive overflow pulses of the second counter during which I.sub.2 is simultaneously integrated with current I.sub.
Abstract: A system for positioning the output shaft of a motor is disclosed having a set of terminals for receiving a predetermined count representing a desired position for the output shaft, a counter having first and second inputs, the first input being connected to the set of terminals, a count generator associated with the output shaft and connected to the second input of the counter for supplying to the counter counts dependent upon the rotation of the output shaft, and a switch connected to the motor and to the counter for energizing the motor when the counter receives a predetermined count representing the new desired position and for de-energizing the motor when the count generator supplies a number of counts equal to the predetermined counts.
Abstract: A digital resolver processor measures the angle of a rotatable device. A resolver connected to the rotatable device generates sinusoidal signals as a function of an excitation signal and of the resolver angle. A phase shift network receives the sinusoidal signals and generates leading and lagging phase shifted signals with a relative phase shift proportional to resolver angle. A counter is enabled by the leading signal and inhibited by the lagging signal so that the contents of the counter represents the relative phase shift, and thus, the angle of the rotatable device. The angular position of the resolver is limited so that the contents of the counter is maintained within a predetermined range in the absence of a fault condition of the resolver terminals. The contents of the counter is forced outside the predetermined range in response to short or open circuit conditions of the resolver terminals, so that misleading angle representations may be recognized as such.
Abstract: An analog switch for an analog-to-digital converter which permits an analog voltage level to be read from a series resistor ladder network and be compared to an external analog signal by a comparator. The incremental levels of the series resistor ladder network are selected by a tree decoder responsive to the comparator output. The analog switch has two transistors, the first transistor being connected between the resistor ladder network and the comparator and being gated by a second transistor and the tree decoder so that the first transistor may be precharged or accessed by the tree decoder.
Abstract: An analog input signal to be converted is subjected to first integration by an integrator and a reference signal opposite in polarity to the input analog signal is subjected to second integration by the integrator. After the integrator output has passed a predetermined level, a reference signal opposite in polarity to the abovesaid reference signal is subjected to third integration by the integrator for a predetermined period of time and then a reference signal of the same polarity as that in the second integration is subjected to fourth integration by the integrator at a rate of an integral fraction of the integration rate in the second integration. In the second integration, clock pulses are counted by a counter but the counting is interrupted for a period of time substantially twice as long as the third integration period and, in the fourth integration, the counting is performed at a counting stage of one lower order.
Abstract: A multithreshold A/D converter has primary and secondary quantizing stages. The threshold reference voltages for the secondary quantizing stages are obtained by amplifying a threshold reference voltage step derived from the primary quantizing stage. Since the secondary threshold reference voltages are derived directly from the primary reference voltages the secondary reference voltages will track deviations occurring within the primary quantizing stage. A reference tracking amplifier is utilized to amplify a portion of the primary reference voltage and apply same to the secondary stage. By using monolithic integrated circuit fabrication techniques to identically match the reference tracking amplifier with the error amplifiers of the primary quantizing stages, the secondary threshold reference voltages will also track deviations in the peak error signals conveyed from the primary to the secondary quantizing stages.
Abstract: A digital to analog converter is provided, for making a digital to analog conversion, and including, an analog to digital converter portion which may be an existing converter, an arithmetic logic unit which is coupled to the analog to digital converter portion, a digital to dc converter portion which is coupled to the arithmetic logic unit, an ac multiplex circuit for an ac operation which is adapted to be coupled to the digital to dc converter portion, a dc multiplex circuit for a dc operation which is adapted to be coupled to the digital to dc converter portion, a switch which couples either the ac multiplex circuit or the dc multiplex circuit to the digital to dc converter portion and which is coupled to and operated by the arithmetic logic unit, and a multiplex control which is actuated by the analog to digital converter portion and which is coupled to the ac multiplex circuit and to the dc multiplex circuit for controlling the output signals from the ac circuit and dc circuit to the analog to digital con
Abstract: The differential linearity of an analog-digital converter is measured by a test method that eliminates the need for precision calibrated test equipment. A triangle waveform with a pseudo random period is applied to the analog/digital converter input. The waveform has a uniform amplitude probability density function. Therefore, any analog/digital converter input voltage has an equal chance of being sampled by the analog/digital converter. The number of times each possible analog/digital converter output code word occurs is counted by a microprocessor. These numbers are a direct measure of differential linearity with an accuracy described by the theory of repeated random sampling.
January 21, 1980
Date of Patent:
September 28, 1982
The United States of America as represented by the Secretary of the Air Force
Abstract: The reference signal output from a reference oscillator is applied to a counter where the reference signal is counted to provide a count output as a changeable digital value. A saw-tooth wave generator is provided so as to generate a saw-tooth wave such that the saw-tooth wave is changeable of the waveform in synchronism with the count output. A comparison voltage generator is also provided which may typically comprise a variable resistor. A load enable signal generator is provided to receive the saw-tooth wave output from the saw-tooth wave generator and the comparison voltage output as set in the comparison voltage generator. The load enable signal generator is structured to compare the saw-tooth wave output and the comparison voltage output to provide a load enable signal whenever both outputs coincide with each other.
Abstract: An apparatus for receiving optically encoded binary data transmitted over an optical fiber from an optical transmitter device coupled to another data processing system. The receiver apparatus is used to convert the light signal carrying the subject data into TTL level digital logic signals. The receiver apparatus is comprised of circuitry for converting the optically encoded data into electrical signals in serial format, and circuitry for converting these electrical signals into TTL level digital signals in parallel format for use by a user device. The primary advantage of the apparatus disclosed here is the ability to substitute a single optical fiber for a plurality of parallel copper wires for carrying data between one data processing device and another with little or no loss in speed due to the larger bandwidth of optical fibers.
Abstract: An autozero loop for eliminating offsets in the analog to digital converter section of a voice frequency coder-decoder (CODEC) utilizing an array of capacitors and a linear resistor string. The autozero loop functions with a relatively small time constant to null offsets quickly during the power-up phase of CODEC operation and with a higher time constant after the power-up phase. A dual bandwidth sub-circuit in the loop is connected to a voltage generator and controlled by signals from a logic circuit to operate at different bandwidths and thus provide different offset cancelling feedback signals during the power-up and normal operating phases.
Abstract: A digital-to-analog converter comprising a plurality of identical transistor current sources with their emitters connected to respective shunt legs of an R-2R ladder network for establishing binary weighting of the transistor currents. The effects of variations in transistor offset voltage are compensated for by returning the ladder termination resistor to a voltage which is 2(kT/q)1n 2 more positive than the last active stage of the converter.