Abstract: A plurality of charge-coupled device shift registers or shift register elements is used to generate a plurality of packets of charge, each proportional to a different reference potential. Using a sense amplifier or comparator, each of the packets of charge is compared, either simultaneously or sequentially, with one or more packets of charge generated by the potential of an analog signal. Signals from the comparator are then supplied to an encoder or a counter to generate a digital signal representative of the analog signal. In one embodiment the plurality of different reference potentials are generated by positioning the shift registers or shift register elements at various locations along a resistance having a potential applied across it.

Abstract: Utilizing a plurality of analog to digital converter cells with transfer gates as implemented by large scale integrated circuit techniques incorporating charge coupled device technology, a 16 bit or larger analog to digital converter is achieved. On a single integrated circuit chip, the necessary A/D cells are formed, whereby in each cell gate and charge packet transfer paths allow for the analog to digital conversion. With transfer gates coupling the A/D cells, the multi-bit A/D conversion register is constructed. Digital voltage levels indicative of logic 0's or logic 1's are generated from varying analog charge levels applied.

Abstract: A digital to analog conversion system includes a memory for storing a plurality of correction codes corresponding to corrections required to compensate for inaccuracy in output currents of a main digital to analog converter (DAC) contained in the digital to analog conversion system. A plurality of the logic inputs applied to the inputs of the main DAC are also applied to the address inputs of the memory. A trim DAC having its inputs coupled to the data outputs of the memory converts the correction code stored in the addressed location of the memory into a correction current which is utilized externally of the main DAC to modify the net amount of output current available from the main DAC to compensate for inaccuracy of the unmodified output current. An output signal from a temperature sensor is connected to a digital number which is also applied to a plurality of the address inputs.

Abstract: A circuit for monitoring the alignment of analog-to-digital converters. The digital output signal from a converter under test is separated into positive and negative component signals which are compared by a subtraction circuit. A difference signal is then generated by the subtraction circuit to represent the required converter adjustment. Also included are adder circuitry for a sum output and provisions for analog display.

Abstract: In an A-D converter of a dual slope system, a digital value set by setting means is provided to switch drive signal generating means to derive therefrom a switch drive signal of a time width corresponding to the digital value, and by the switch drive signal a switch is turned ON, through which a constant voltage is superimposed on an analog input voltage.

Abstract: A solid state synchro torque receiver driver that uses unfiltered AC as the power source and push-pull regulating transistors operating in the linear mode to drive the torque receiver stator loads. A feedback amplifier compares the push-pull outputted AC signal against an inputted AC data reference (i.e. the desired stator excitation amplitude) and thus closes the loop forcing the output to follow the input. The synchro torque receiver operates in a closed loop and thus has realizable potential of near infinite resolution and high accuracy.

Abstract: An analog-to-digital converter of the integrating type is disclosed in which, while an analog input signal is integrated over a first period, a reference signal is selectively superposed on the analog input signal during the first period when the integrated value exceeds a predetermined value, so as to reduce the absolute value of the integrated value of the analog input signal, and then at the termination of the first period the integrated value is inversely integrated by a reference signal (a separate reference signal or the same reference signal as above-mentioned), a period within the first period during which the reference signal is superposed and the second period, i.e., from the beginning of the inverse integration after the first period to the time point that the integrated value reaches the predetermined value being used to produce an output in a digital form.

Abstract: Two-phase logic signals from a reversible shaft encoder or like device provide count occurrence pulses and a count direction logic signal to control incrementing and decrementing of a counting means. One count occurrence pulse is omitted each time the count direction changes to avoid errors which otherwise might result. Up counts and down counts occur at the same shaft encoder positions, and the system has high noise immunity.

Abstract: An indicator arrangement includes comparators for parallel comparison of an analog input voltage with digitalizing standard voltages to digitalize the input voltage and an indicator for indicating digitalized output. The arrangement is provided with a controller periodically switched between a first control state and a second control state. The controller in the first control state allows the comparators to perform comparison in a first voltage range of the analog input voltage while in the second control state it allows the comparators to perform comparison in a second voltage range of the analog input voltage.There is provided an encoder for coding the digitalized output of the comparators with a first coding mode in the first control state of the controller and coding the digitalized output of the comparators with a second coding mode in the second control state. The encoder is adapted to drive the indicator with a first or second mode according to the state of the controller.

Abstract: A combination of integrating and logic means in an electrical circuit responds to inputs from a variable analog control signal and from a constant frequency train of digital pulses. The magnitude of the control signal is variable between predetermined low and high extremes. The logic means periodically generates discrete output signals in synchronism with the digital pulses. When the control signal is lower than a predetermined intermediate magnitude, the integrating means is saturated and the logic means is able to produce the output signals at a constant frequency. When the control signal is between its intermediate and high extreme magnitude, the integrator is active and governs the operation of the logic means in such a manner that the average frequency of the output signals varies between its constant magnitude and zero as an inverse linear function of the control signal magnitude.

Abstract: The value of three components of an analog signal are compared with zero and in two's compared with one another. Each possible combination of the comparison result, within the range of possible phase argument values of the analog signal, has correlated therewith a respective zone, whereby there is formed a coarse interpolation of a period of the analog signal into phase zones. The components are digitized and there are selected the components having the smallest (X), the intermediate (Y) and the largest (Z) absolute value. There are formed the digital functions H=Y-X and K=Z-Y+X. Each possible combination (H, K) is correlated to a respective predetermined number of steps of the phase argument within the zone, thereby producing a fine interpolation of the zone into steps. Preferably, at the beginning there is substracted from each analog component one-third of the sum of the three components.

Abstract: An integrating analog-to-digital converter particularly adapted to measure inertial instrument outputs for strap-down navigation. In the converter, an input signal is summed with a number of precisely quantized voltage pulses and is integrated. An error signal at the output of the integrator controls the rebalance duty cycle of the converter. Counting the net rebalance quanta over an interval results in an output count which is proportional to the input signal voltage.

Abstract: An analog-to-digital and digital-to-analog conversion system utilizes a modified delta modulation technique, together with generation of a number of linear waveforms forming a piecewise linear approximation of an analog signal to be encoded and decoded, to digitize the analog signal as a pulse train and subsequently retrieve an approximation of the original analog signal from the pulse train. The system comprises encoder and decoder sections of near identical structure. The encoder section includes compare circuits that compare the signal to be encoded to a reference signal and generate therefrom a binary indication of such comparisons. Successive ones of the binary indications form the digital pulse train containing information later used to approximate the analog signal being digitized.

Abstract: The constant-current circuit consists of two MISFETs connected in series and a gate bias circuit for these MISFETs. The drain voltage of the first MISFET is maintained substantially constant by the source voltage of the second MISFET. The first MISFET does not sustain the channel length modulation, because its drain voltage is substantially constant. Consequently, a constant output current is obtained through the drain of the second MISFET.

Abstract: A charge transfer analog-to-digital converter is provided with means to establish the potential across a large storage well at a comparator threshold voltage at the initiation of a cycle. Charge transfer circuitry is also provided for transferring, into the large potential well, charge packets of size dependent only upon the value of a charge packet capacitance and a scaling voltage. Parasitic capacitance effects are essentially eliminated.

Abstract: A non-uniform weighting circuitry which is effective for enhancing speed and accuracy in the operations of encoders and decoders comprises in a cascade connection a constant current switch, a variable attenuator, a polarity changing circuit and a uniform weighting circuit. An impedance converting means is provided to make at least one of input and output terminals of the variable attenuator to be of low impedance, whereby spike-like noises generated by a switching element constituting a part of the variable attenuator is reduced.

Abstract: The conversion of an analog signal which varies over a wide dynamic range, to digital form is accomplished by integrating the analog signal and, simultaneously therewith, integrating in a sense opposite that of the analog signal a reference signal of sufficient amplitude, to maintain the stored charge within the integrator at a relatively low nominal value. This is accomplished by placing comparators on the output of the integrator which function to cause a counter to count up or down in accordance with the relative amplitudes of the analog and reference signals as is necessary to bring the stored charge in the integrator back to the low nominal value. The output of this counter is applied to a range decoder which applies selected geometrically varying ranges of digital signals to a digital to analog converter. The output of the digital to analog converter is applied both to the subtracting or negative input of the integrator, and also provides a reference signal for the comparator.

Abstract: A digital attenuator to stepwise modify multiple controlled signals including generator to provide counter signals at selected frequency, a counter to count the signals having multiple counter outputs to provide a counter output signal when activated and adapted to selectively activate each counter output in selected sequence in response to selected numbers of counter signals so the counter provides a repeated pattern of output signals at the output means to provide a counter output control cycle, multiplexer having a selected number of multiplex signal inputs each adapted to receive binary input signals from selected signal generator multiplex control means to selectively connect each of the multiplex inputs is connected to the multiplex outputs during each counter output control cycle, signal storage device having an input connected to the multiplex outputs to store the multiplex output signals to provide a stored binary signal indicative of the sum of the number of multiplex output signals received during

Abstract: An electronic angular coder for theodolites or the like, comprising a rotng disk bearing a series of engraved radial markings, a stationary detector, and a mobile detector. An approximate measure of the offset angle between a stationary detector and a mobile detector is accomplished by counting the markings passing in front of the heads. Fine measures of the shift in phase between the passage of a marking in front of the mobile detector and the fixed detector are also obtained.

Abstract: A data processor includes a base register for a base address modification and a program counter for a relative address modification. An instruction executed in the data processor includes an operation code, a first operand, an address modification judgement bit, an index address modification field, a base address modification field and a displacement. When the instruction is fetched, it is arranged in an address modification and a base modification according to the address modification judgement bit. In the case of the relative address modification, the contents of the program counter is added to the contents of the displacement. In the case of the base address modification, the contents of the base register specified by the base address modification field is added to the contents of the displacement.