Abstract: Data acquired from a source such as a coded disc is processed so as to be free of ambiguities associated with boundary transitions where the data source produces groups of bits which have least significant ordering and higher significant ordering. Wherever a common transition boundary between the bit groups occurs, ambiguities from misalignment of these boundaries are avoided by controlling the higher ordered bit transitions from the lower ordered bit transitions. Circuitry tracks and stores the higher order bits by synchronous updating whenever no misalignment or skew sensitive transitions are encountered. Logic circuitry continuously inspects the lower significant bits to determine the presence or absence of a zone surrounding the common transition boundary and also detects the actual passage and direction of the transition boundary in the lower significant bit group. This logic corrects the counter stored higher order bit counts in conformity with the status of the lower significant bit states.

Abstract: A digital delay line for an analog signal having an improved efficiency in converting between the analog and digital signal formats. The delay line operates by converting an analog output into a representative series of binary ones and zeros which are applied through a shift register at a set clock rate. The shift register output, at a selected delay interval, is reconverted to the original analog levels. The conversions are governed by a logic network which increases the conversion efficiency to permit a lower clock rate and shorter shift register without a corresponding loss in frequency response.

Abstract: To permit a cook to easily adapt an existing recipe, a calculator includes logic circuitry for calculating and storing the ratio of servings desired to servings stated in the recipe. The calculator also includes a keyboard for entering the quantity of each ingredient stated in the recipe. Desired units of measure and stated units of measure can be entered through marked keys. The calculator converts a stated quantity in the stated units to the amount required for the desired number of servings in the desired units of measure. The results are displayed on a visual display.

Abstract: An analog to digital converter includes a first parallel comparator network receiving the analog signal and continuously producing the most significant bits of the digital signal, a subtractor for removing from the analog signal the amplitude portion corresponding to the most significant bits, a second parallel comparator receiving the modified analog signal and continuously producing the least significant bits of the digital signal, and a sampling buffer responsive to a sampling pulse to provide the digital signal only at the occurrence of the sampling pulse.

Abstract: A serial digital-to-analog converter using charge-coupled device technology. The converter comprises, in tandem, an input charge source diffusion, an input charge storage gate, a pair of charge splitting gates and an output charge collecting diffusion. The diffusions and the charge storage and the charge splitting gates are separated from each other by respective control gates.

Abstract: A digital to analog resolver converter uses a digital to analog converter to convert a part of the digital input to a corresponding analog angle value. This analog angle value is applied to sine and cosine function generators which use bits of the digital input signal to select slope and intercept values for approximating the sine and cosine of the analog angle value. The outputs of these function generators are applied to an octant select circuit, which chooses the values to be used as the sine and cosine of the angle in a particular octant. Two circuits then assign the proper sign to the cosine and sine function values.

Abstract: A digital-to-analog converter using a combined pulse rate and pulse width modulation of an output signal of a circuit for providing a digital signal to be converted to a periodically occurring series of digital comparison signals to be obtained by a proper choice of a particular series. The digital-to-analog converter has a very small error which, due to its low temperature sensitivity, is particularly suitable for tuning circuits of television receivers.

Abstract: A reading system for a hybrid A-D converter having, in combination, code disk A-D converters for converting an analog quantity such as a rotation angle or the like into a digital quantity and a neighborhood absolute value detector such as an inductosyn, a resolver or the like for providing the absolute value of a rotation within a small range thereof to, thereby extend the neighborhood absolute value region. Each of the code disk A-D converters supplies an output signal l and a carry signal Cr(1) which is generated depending on whether an output signal from a lower order code disk A-D converter is included in a predetermined upper group to a corresponding one of the logical circuits which are provided so as to correspond in number to the code-disk A-D converters. The logical circuit performing the logical operation L = l .multidot. (Cr.multidot.l-1+Cr.multidot.l+1) provides a signal representative of one digit whereby the outputs from the A-D converters are prevented from errors upon carrying.

Abstract: An improved method and apparatus are disclosed for the reading (or sensing) and decoding of two frequency "bar coded" or transition coded sensible data. The data may take the form of indicia recorded on various media or it may be transmitted on a communications channel. The method and apparatus include means for simultaneously or separately accommodating both variable velocity scan (or distorted reception) conditions and non-uniform bar widths in the coded data or other variations in the spacing of transition signals in the recorded indicia. Frequency variations in transmitted data signals can also be accommodated. Hand held sensor or "wand" scanning of coded tangible indicia-bearing media is facilitated for either optically or magnetically recorded data indicia. Correct interpretion of frequency-distorted transmitted data is also made possible.

Abstract: A digital-to-analog converter method and apparatus is disclosed which utilizes a hybrid technique of combined pulse width and pulse rate modulation to achieve improved performance with reduced logic and circuitry requirements. Lower order bits of an N-bit digital data input for conversion to a corresponding analog output voltage level are treated in a manner similar to pulse rate modulation approaches utilized previously. High order bits are handled together in a variant form of pulse width (duration) modulation in which the pulse width required to generate the given analog voltage level corresponding to the high order digital bit inputs is divided into a fixed number of slices in a given sample time, each slice having a width or duration of pulse output which is variable in itself in correspondence to a function of both the high and low order bit value inputs. A low pass filter or integrator combines all of the pulses in a given sample to produce the analog voltage level output.

Abstract: The holding integrator of the arrangement, which integrator is to integrate the signal to be encoded during time intervals T.sub.1 = pT separated by time intervals T.sub.2 = qT in the course of which the integrated value is to be memorized for comparison with one or two ramp signals, comprises a charge transfer device with (p+q) stages receiving advance signals having a period T. The signal to be encoded is applied to the injection circuit of the charge transfer device during the intervals T.sub.1 while a zero voltage is applied thereto during the intervals T.sub.2.

Abstract: A digital to analog converter is disclosed wherein two current outputs are provided, one the complement of the other. The digital to analog converter includes a novel two branched, symmetric, transistor switching circuit as well as an improved electrical n-bit weighting network which has ports for communicating weighted signal segments to connected transistor switching circuits. Logic inputs to the switching circuits determine whether an output signal is to be supplied in a first output summing line or a second, complementary, output summing line, both of which have high output impedance and high output voltage compliance which defines true current output.

Abstract: A digital indication for a selectable impedance circuit consisting of a plurality of serially connected impedances and a selector which is connectable to a common junction of any of them is provided by connecting an electric signal source to the end terminals of the circuit to develop a signal between the selector and at least one of the end terminals which is compared with the output of a digital/analog converter, the converter being connected to the output of a digital counter which continues to receive clock pulses until disabled from doing so by a comparison difference within a predetermined tolerance.

Abstract: A P.C.M. compression-law coder in which sample values in different segments of the dynamic range of the coder are allotted different charging time intervals in an integrator circuit, the segment number forming one part of the resultant encoded signal and digital measure of the discharge time of the integrator circuit at constant current providing another part of the encoded signal.

Abstract: In an analog to digital converting circuit used in a pulse height analyzer or in a time to digital converting circuit used in a time analyzer, the first binary in a scaler for counting clock pulses is switched over to use the true state and the complementary state each of the reset circuit and the output circuit, alternately. By switching over the reset circuit and the output circuit, no substantial variation in counting the scaler is induced and any odd-even unbalance phenomena due to the binary constitution of the scaler is statistically equilibrated.

Abstract: A circuit, for producing direct voltages, for example the tuning voltages for a television or radio receiver, lying within a direct voltage range from pulses fed to an integrating circuit at whose output the direct voltages appear. A plurality of pulses (I) are fed to the integrating circuit, at whose output the direct voltage (U.sub.I) appears, within a period duration (T) assigned to the desired direct voltage range, with the period duration (T) being at least of the magnitude T = (U.sub.max - U.sub.min) .multidot..DELTA..tau./.DELTA.U.sub.I, where (U.sub.max - U.sub.min) is the desired direct voltage range, .DELTA..tau. is the shortest time duration of a pulse (I) and .DELTA.U.sub.I is the smallest voltage step width associated with the shortest pulse duration .DELTA..tau. by which two different direct voltages (U.sub.I) at least differ from one another.

Abstract: In an encoder portion, a communication system converts analog signals, into linear delta modulated (hereafter LDM) signals and LDM signals into compressed pulse code modulated (hereafter CPCM) signals while in a decoder portion, the system reconstructs the CPCM signals into LDM signals and then analog signals substantially corresponding to those originally input into the system.

Abstract: In one exemplar embodiment, a digital altitude encoder is provided that utilizes a conventional altimeter responsive to atmospheric pressure for rotationally driving an indicator shaft. Attached to the shaft is a disc having repetitive, alternate, regularly disposed solid portions and slots. A light source and a pair of light detectors for receiving light from the source are spaced adjacent the disc to permit one of the detectors to generate a first signal and the other detector to generate a second signal having a relative time of occurrence dependent on the direction of the rotation of the disc. A counting means that is presettable to a predetermined digital count representative of a preselected altitude function receives the first and second signals and increments or decrements the predetermined count in response to changes in altitude.

Abstract: An analog-to-digital integrator utilizing a voltage to pulse frequency converter which has an analog integrator that charges and upon exceeding predetermined thresholds provides an output pulse and simultaneously discharges the integrator for a predetermined time. The output pulse also actuates a serial adder which sums a scale word with the previous accumulated result; this accumulated result is the digital word output of the integrator.

Abstract: Apparatus for generating synchronized multi-axis intermittent motion utilizing electronic encoding, memory and a servo controlled positioning system. A plurality of mechanically independent slave shafts are positioned in response to the position of a rotatable master shaft. An analog transducer is attached to the master shaft providing an analog output signal which is fed through an analog-to-digital converter. A digital representation of the master shaft position is provided by the analog-to-digital converter. The digital indication of master shaft position is fed to a plurality of independent digital memory devices each of which provides, in response, a digital position signal indicative of the desired position of an associated slave shaft. The output of each independent digital memory device is fed to a digital-to-analog converter which provides an analog output representative of the desired slave shaft position. A servo controller positions the associated slave shaft in response to the analog signal.