Abstract: A circuit for the decoding during reading of data prerecorded on a magnetic medium comprising a circuit for recognition of the recording code of the data recorded on the support by the recognition of the frequency of an input signal generated during the reading of the support and a frequency generating circuit controlled by the recognition circuit for generating a signal of predetermined frequency for the conversion of the recording code recognized into a binary code. A read-only memory comprising two zones is responsive to the recognition means for generating correcting words applied to a counter for controlling the position of a decoding window generated by a phase locked loop oscillator.

Abstract: A PCM codec for converting between PCM words and analog signals has at least one element which is used for both types of conversions even though the clock pulse frequencies of the incoming and outgoing PCM words are different; a timing unit for generating time intervals wherein a first and second number are needed at the very most to carry out the respective conversion operations, the shorter of the period lengths determined by the two clock pulse frequencies includes at least the sum of the two numbers of time intervals; and a control unit for receiving the clock pulses in order to indicate the respective conversion type and for generating conversion type signals by means of which each of the time intervals is associated with one of the two conversion types. In order to control states where a type signal is generated delayed with respect to a notification pulse, the codec includes information memories to store the influenced information.

Abstract: Circuitry useful in PCM coders for effectively shifting the idle channel noise signal to a level midway between the code state boundaries thereby significantly reducing the likelihood that noise signals will cross a boundary and be encoded.

Abstract: There is disclosed a trim network suitable to be utilized in monolithic circuits and a method of trimming thereof to improve performance of the circuits to achieve greater yields. The network comprises at least one monolithic resistor connected across a known voltage potential and including a plurality of contacts thereon defining incremental resistances therebetween. The contacts are coupled to a common terminal via a plurality of metallic links. A desired output voltage is derived at the common terminal by open circuiting all of the links but a desired one. The voltage appearing at the common terminal can then be used for trimming a parameter of the monolithic circuit to improve the performance thereof.

Abstract: An MOS integrated circuit digital-to-analog converter employing a plurality of generally parallel resistance strings. Decoding means and switching means provide an analog output from the resistance strings, this output passes through only two switches. The resistance strings may be closely fabricated on a substrate, thereby reducing the effects of processing variations. A unique layout for the converter array minimizes the effects of masking misalignments.

Abstract: A system for processing cyclic signal pairs generated by an optical transducer to provide an accurate measurement of the displacement of one member with respect to a reference is suitable for determining weight by measuring spring scale tare deflection. The system includes a pair of comparator Schmitt trigger circuits for shaping pulse waveform signals. The pulse signals are processed by fully clocked digital circuits including edge discriminators to generate multiple count pulses which are processed by combination logic for direction determination. Further processing includes sign determination (positive-negative) and zero identification circuits to provide up and down pulses which are filtered and fed to up/down counter stages. Counter stage information is decoded for feedback control and processing logic indication.

Abstract: Analog-to-digital converter, comprises a measuring amplifier circuit, a comparator, a counter, a digital-to-analog converter, a feedback circuit and an offset correction circuit, and is operative in three modes; one mode for adjusting the gain factor of the measuring amplifier circuit by means of the feedback circuit, one mode for offset correction of this measuring amplifier circuit by means of the offset correction circuit and one mode for measuring a supplied voltage for conversion into a digital value.

Abstract: A device for the acquisition and storage of an electrical signal.The signal is divided into adjoining elementary time intervals of specific duration. During each of them the amplitude minimum and amplitude maximum of the signal are established, which values are first stored in analog form and subsequently in digital form.The device may be utilized in oscilloscopes, in particular those of the type comprising a matrix display panel.

Abstract: An analog-to-digital converter includes an integrator which includes an amplifier having an offset voltage. A counter is responsive to a counter clock signal for counting during the duration of a first integration and transferring its count at the end of the first integration to a storage circuit. The counter is then reset. It then counts during the duration of a second integration. Coincidence circuitry is provided which causes the counter to be reset during the second integration when its count matches the count stored in the storage circuit. The counter then continues counting until the end of the second integration. The uncertainty associated with the count stored in the counter at the end of the second integration is improved by provision of a circuit responsive to the comparison signal and first and second clock signals for producing the counter clock signal.

Abstract: An integrated-circuit 12-bit digital-to-analog converter comprising binarily-scaled constant-current sources with associated switch cells employing bipolar transistors to direct the bit currents either to a summing bus or to ground. The switch cells include a first differential transistor pair to translate a single-ended binary logic signal to double-ended (balanced) format, and a second, fully-balanced differential pair operated by the balanced logic signal to direct the bit current correspondingly. A bias-generating circuit maintains a constant collector-base voltage at the constant-current source. The threshold voltage for the logic signals can be set for TTL logic or, by pin-programming, for CMOS logic of either low-voltage or high-voltage type.

Abstract: This digital-analog converter receives a digital number and applies it to a counter capable of handling an n-bit binary capacity. When the counter counts to its full number, e.g. 1111 for a 4-bit capacity a writing signal generated in a control section causes the complement of the applied number to be written into the counter. The counter is then able to start counting from this complement number to the full (1111) number again. The control section then complements the written-in number back to the original number and counts up to the full number yet again. Thus, if the original binary number is 1100 and the reverse number, the counter counts 1100 and 0011 repetitively. At each count reversal, a flip-flop reverses, and a pulse corresponding in length to the original number is produced within each full count interval and that pulse is filtered by a low-pass filter to produce an analog signal corresponding to the original digital one.

Abstract: A preamplifier using charge transfer techniques is formed on the same chip as a charge transfer analog to digital converter. The preamplifier then couples low level output sensors directly to the converter without need for a costly interfacing amplifier.

Abstract: The outputs of individual stages in a digital to analog converter are each trimmed by independent circuitry which includes a plurality of transistors connected to a common output terminal, the physical dimensions of each transistor being scaled in proportion to desired levels of current flow, and selectable switches connected in circuit with each of the transistors. Selectable switches are actuable to produce an output trimming current of a desired magnitude, which current is used to correct the untrimmed stage output. The invention includes circuitry for controlling the polarity of the trimming current relative to the stage, and for selectively expanding or contracting the trimming range to optimize the trimming currents for the particular characteristics of the converter. A favorable balance between trimming accuracy and the area occupied by the trimming circuitry is attained by the use of both emitter-scaled and multicollector transistors in the trimming circuits.

Abstract: A semiconductor charge coupled device (CCD) is provided with an array of auxiliary charge storage sites of successively decreasing binary digital storage capacities (1/2, 1/4, 1/8, 1/16, etc.) along the CCD propagation direction. These auxiliary sites sequentially subtract, from a propagating analog signal charge packet, successive amounts of charge ("1") vs. no charge ("0") corresponding to the presence vs. absence of correspondingly sufficient charge in the propagating analog packet. The resulting sequence of "1"'s and "0"'s provides a digital representation in the binary system of the analog signal charge packet.

Abstract: An absolute resolver digitizer for a numerical control system generating a digital number indicative of the absolute angular position of a resolver's rotor within a given revolution is disclosed herein. The resolver digitizer comprises a reference generator generating resolver excitation signals and a digital number indicative of the phase of the generated excitation signals and a resolver follower generating a digital number indicative of the sum of phase of the excitation signal generated by the reference generator and the angular position of the resolver's rotor. Subtraction of the digital number generated by the reference generator from the digital number generated by the resolver follower produces a digital number indicative of the resolver's absolute position within a given revolution. This subtraction may be performed by a separate circuit within the absolute resolver digitizer or may be performed by the computer associated with the numerical control system.

Abstract: In an analog to digital converter in which each sampled portion of an incoming video or other analog signal is converted to a digital character in a plurality of parallel conversions occurring serially; the range of the voltage level reference signals of descending magnitude which are applied to comparators for effecting a relatively fine parallel conversion of a sampled analog signal is selected to be larger than, and offset in respect, to the steps or increments of the voltage level reference signals of descending magnitude which are applied to comparators for effecting a preceding relatively coarser parallel conversion, and the encoded outputs from the serially occurring parallel conversions are digitally added with the least significant bit of the encoded output from each preceding relatively coarser parallel conversion being accorded the same weight as the most significant bit of the encoded output from the next following relatively finer parallel conversion so as to eliminate from the result of the digi

Abstract: Novel apparatus is described for controlling the application of circuit adjustment signals to an electrical circuit device. The same device leads are used in an operating mode with input signals in a first range, and in an adjustment mode with input signals in a second range, the two ranges being mutually exclusive.An exemplary embodiment is directed toward trimming a digital to analog converter. A plurality of trimming elements are provided with an equal number of two-terminal actuating devices, which are arranged in a matrix such that each pair of terminals is connected in circuit with a unique pair of input leads. The devices actuate their associated trimming elements in response to the application of actuating signals, exceeding a threshold level greater than the level of the binary input signals, to their respective lead pairs. The leads are thereby capable of a dual mode operation, with one mode for normal converter operation and the other mode for setting up desired trim circuits.

Abstract: A wide dynamic range, wide bandwidth, analog-to-digital conversion system d method. A plurality of overlapped analog-to-digital converters are utilized in conjunction with scaling amplifiers to provide a plurality of output ranges. Means for selecting the set of output bits which provides a magnitude representation of the input signal are provided along with means for outputting a digital representation of the appropriate range.

Abstract: A high resolution digital angle encoder for determining the angular position of a first shaft with respect to a reference position. A signal generator operates through a three-stage counter to provide an excitation signal to a motor which turns a second shaft. The second shaft cooperates with a reference position detector and a shaft position detector to respectively initiate and terminate the storage of the counts of the three-stage counter in a storage register.

Abstract: An electronic order pricing system including a data card having a plurality of item lines, each representing an orderable item with certain of the lines bearing indicia representing a quantity of items ordered by a customer, apparatus for reading the data card line by line and providing outputs representing the data thereon, circuits for calculating the quantity of each item ordered, a programmable price select matrix storing price data for each orderable item, circuits for using the stored price data and the item quantities calculated to calculate a total price for the items ordered, a sales tax based on the total price and a total order price, and circuits for effecting printout of the calculated price data on the data card.