Abstract: The disclosed analog to digital converter employs a single signal propagation path thereby necessitating only one holding capacitor (101) per stage (STAGE 1) of coding. The first terminal (B) of each holding capacitor (101) is connected to a reference voltage (L1) such as a resistive divider (106, 116, 126, 136, 146, 150, 151, V.sub.HI) which has binary weighted taps (L1-L5). The other terminal (A) of each holding capacitor (101) is connected to the analog signal input (INPUT). The reference voltage (L1) and the analog sample (V1) are compared and, for a zero decision, the stored analog sample (V1) is directly passed on to the subsequent stage (STAGE 2) by a buffer circuit (102). For a one decision, the aforementioned first terminal (B) of the holding capacitor (101) is switched from the tap of the resistive divider to circuit ground thereby subtracting that binary weight (L1) from the signal (V1) stored on the holding capacitor (101).

Abstract: An automatic means for decoding a wide data range of Manchester code data. Variable delay means are provided for the Manchester code decoder which are digitally controlled in response to the output of a data rate sensing circuit that provides a digital equivalent of the sensed data rate. The digital equivalent of the sensed data rate is used to optimize the amount of delay in the Manchester code decoder for the particular data rate of the data being received.

Abstract: An electrooptical analog-to-digital (A/D) converter. A laser beam is coupled into a waveguide which has been fabricated on an electrooptical crystal such as a lithium niobate LiNbO.sub.3 crystal. Electrodes are placed relative to the waveguide to form an electrooptical prism and an analog signal is fed to the electrodes. A modulated laser beam passing through the electrooptical prism is deflected in the plane of the waveguide in proportion to the applied analog signal. The deflected beam is expanded in the y-direction by diffraction-spreading or by a beam-spreading lens and falls on a ribbon-fiber, coded detector array. The array effectively codes the analog signal, translating the position of the deflected beam into a coded digital word which is representative of the magnitude of the analog signal.

Abstract: A signal converting circuit for converting an analog signal to a digital signal, or vice versa, comprises a sampling capacitor which is charged to an input signal level during the period of a sampling pulse. A reference capacitor grounded at one end receives charges from the sampling capacitor in response to a first clock pulse. A predetermined reference potential is impressed on a terminal of the sampling capacitor at the time of the sampling pulse and a ground potential at the time the sampling pulse is not present. The reference capacitor is charged in response to the first clock pulse, and is discharged in response to a second clock pulse which alternates with the first clock pulse. The presence of a potential at the sampling capacitor less than the predetermined reference potential is detected, and the cycles of discharging of the reference capacitor that occur until the potential at the sampling capacitor is less than the reference potential are counted.

Abstract: An analog-to-digital converter of the type including a sample-and-hold circuit for sampling an analog signal during predetermined cycles to produce periodically sampled voltages, a source of reference voltages for supplying plural quantizing voltages having a quantizing voltage step .DELTA.V, a plurality of voltage comparators for receiving each sampled voltage and the plural quantizing voltages to compare the sampled voltage to respective ones of the quantizing voltage for determining the level of the sampled voltage relative to the quantizing voltages, and an encoder responsive to the voltage comparators to produce a plural-bit code as a function of the determined sampled voltage level.

Abstract: A charge transfer circuit of the type including first and second capacitors separated by a charge transfer MOSFET is disclosed. The disclosure includes the description of a circuit which compensates for variations in the threshold voltage of the charge transfer MOSFET such that the magnitude of the charge packet transferred from the first to the second capacitor is substantially independent of changes in the magnitude of the threshold voltage.

Abstract: An analog-to-digital conversion circuit having a number of series-connected stages, each stage determining the difference between a signal current input and a reference current input, and at positive values of said difference transferring a current proportional to said difference to the succeeding stage. In each successive stage, the reference current is subtracted from the signal current until the residual current is smaller than the reference current. The number of successive stages in which this subtraction takes place can be detected to indicate the level of the input current.

Abstract: An integrated circuit digital-to-analog converter circuit of the binary weighted current summing type in which the emitter potentials of the transistor current sources are maintained substantially equal by controlling the voltage differential between the base electrodes of the current source transistors. In one disclosed embodiment, the base electrodes of the transistor current sources are connected to a resistive divider network and the voltage across each of the resistors is maintained substantially equal to (kT/q) ln 2. The disclosed circuit can be used as an alternative to, or in combination with, prior art emitter-scaling techniques.

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract: A two-bit analog to digital conversion apparatus for direct and instantaneous generation of digital signals which are independent of the absolute amplitude of the input signal envelope.

Abstract: A temperature-compensated antilogarithmic converter has a temperature-sensitive signal generator for generating a temperature dependent signal which varies in proportion to absolute temperature; a multiplying means for mixing and converting the temperature dependent signal and an input signal into a product signal; and a non-temperature compensated antilogarithmic amplifier for converting the product signal into a non-temperature compensated antilogarithm of the product signal, wherein by placing the temperature-sensitive element of the temperature-sensitive signal generator and the antilogarithmic element of the antilogarithmic amplifier at the same temperature, the dependance of the antilogarithmic amplifier is temperature compensated by the temperature dependent signal. Thereby, an output converted signal the voltage or current of which is stable with respect to temperature variation can be generated.

Abstract: An improved synchro to digital tracking converter which utilizes an approximation to generate information octally and uses digital complementing to generate information over the balance of the quadrant is implemented using a single ladder network to provide a system having fewer components and yet a higher intrinsic accuracy.

Abstract: Analog to digital converter of the type in which an analog input signal is integrated and charge is applied to the integrating capacitor in predetermined measured quantities to offset or balance the effect of the input signal. A counter is incremented and decremented in accordance with the balancing charge to provide a count corresponding to the input signal. Means is included for eliminating errors due to offset voltages and imperfections in the virtual ground of the integrator, and the operating level of the integrator during a conversion is set independently of the sources which supply the balancing charge.

Abstract: In the camera disclosed, depending upon whether the shutter preference or aperture preference mode is selected, a computer establishes a computed value on the basis of a preset value and other ambient conditions. A number of separate comparators compare the respective values to a single reference wave form and turn off respective gates when the analog voltages achieve predetermined relationships to the reference wave form. The gates passed pulses from a common source from the beginning of the reference wave form until the respective gates are shut off. The values are thus digitized and displayed within the camera.

Abstract: An improved method and a circuit arrangement for converting an analog quantity into a digital quantity of the type where the analog quantity is fed to an integrating circuit, to which a reference quantity is temporarily connected during a conversion period and in which the pulses delivered by a pulse generator are also fed to a counter during the time when the reference quantity is connected to the integrating circuit in which during the first phase of a conversion period the analog quantity is fed to a first integrator and, during a second phase immediately following the first phase the analog quantity is fed to a second integrator, with pulses counted in a counter common to both integrators while the reference quantity is connected. Using two integrators permits connecting the analog quantity alternately to each of the integrators and connecting the reference quantity to the respective integrator in the time between, when the analog quantity is not connected.

Abstract: In an illustrative embodiment of the invention, an angular digital-to-resolver data converter apparatus is provided for converting a digital input signal representative of angular data into digital pseudo sine and cosine output signals representative of the angular data, which when converted into analog signals may be used to provide excitation to analog servo system resolvers. The digital or binary output signals which approximate the sine and cosine function of the digital angular data input signal are related such that the ratio of the digital output signal representative of the pseudo sine function to the digital output signal representative of the pseudo cosine function equals the true tangent of the actual angle.

Abstract: In a digital to synchro/resolver converter which has an intrinsic transformation ratio variation with respect to input angle greater than desired in a given application, the intrinsic variation is corrected by applying a correction to the reference voltage used in carrying out the digital to synchro conversion.

Abstract: A digital-to-analog converter in which a comparison of a digital signal combination to be converted with a signal combination produced by a counting circuit is implemented serially for minimizing the number of connections in the circuit.

Abstract: An analog-to-digital converter of the ramp-integrator type utilizing a special technique to reduce errors due to offset voltages. The integrator first is ramped up and then back to a reference level, by sequential application of opposite-polarity reference signals. A digital determination of net offset error then is made by comparing the total time of ramp-up-and-back with a fixed time period set by a clock generator. During the subsequent conversion operation, integration of the analog signal is controlled in accordance with the amount of net offset error so as to provide a feed-forward error correction. Integration is always in the same direction away from zero for analog signals of either polarity, thus avoiding the effects of discontinuity around zero input.

Abstract: A digital data transmission rate of three bits per cycle of bandwidth is achieved in precoded partial-response band-limited communication channels by partitioning binary digits into groups of three two-level digits and translating these binary groups of three into pairs of three-level digits prior to transmission. Correct pairwise association of received signals is accomplished by reserving a three-level digit pair for monitoring purposes. This reserved pair can validly occur only at a transition between allowable pairs. By monitoring the presence of the reserved pair, correct pairwise association of ternary digits is assured and binary digits are properly decoded without having to provide a special framing signal.