Abstract: A fiber-channel loop interface circuit that includes a dedicated transmit-frame buffer for loop initialization and responses (“responses” are non-data frames sent in response to commands or inquiries from other nodes). Having a dedicated transmit-frame buffer allows one port of a dual-port node to be transmitting initialization or response frames while another port is transmitting data frames, response frames, or initialization frames. Either or both ports can also be simultaneously receiving frames. The system includes a channel node having dual ports, each supporting a fiber-channel arbitrated-loop serial communications channel, and dedicated frame buffers within the channel node for loop initialization and responses. In some embodiments, the dedicated frame buffers are configured as on-chip buffers and include: two inbound non-data buffers coupled to the two ports, a data-frame buffer coupled to both ports, and an outbound transmit-frame buffer coupled to at least one of the ports.

Abstract: A system stream contiguous reproduction apparatus to which are input one or more system streams interleaving at least moving picture data and audio data, and system stream connection information includes a system clock STC generator for producing the system clock that is used as the system stream reproduction reference clock. The system stream contiguous reproduction apparatus further includes one or more signal processing decoders that operate referenced to the system clock STC, decoder buffers for temporarily storing the system stream data transferred to the corresponding signal processing decoders, and STC selectors for selecting a system clock STC referenced by the signal processing decoders when decoding the first system stream, and another system clock STC referenced by the signal processing decoders when decoding a second system stream reproduced contiguously to the first system stream.

Abstract: A computer system's BIOS (basic input/output system) POST (power-on self test) sets a bit or bits in an ISA (industry standard architecture) I/O (input/output) port, in a memory, or in a scratch pad register accessed via an ISA I/O port (indexed or non-indexed), that an AML (ACPI control method machine language) in the DSDT or other ACPI tables can access. These bit(s) will be set depending upon SETUP program selections or different hardware configurations detected by the BIOS during POST. The AML, which is the compiled result of ASL (ACPI control method Source Language) code, returns back different values for the lowest system sleep state depending upon the bit value(s) read from the ISA I/O port, the memory or the scratch pad register accessed via the ISA I/O port. In addition, an ASL code allows an external agent, e.g., an application program, to modify the ISA I/O port, the memory or the scratch pad register accessed via the ISA I/O port.

Abstract: A clock control technique allows reducing the power consumption of devices connected to a computer bus. Individual idle devices can be disconnected from the bus clock by a device clock controller and placed in a low-power state without waiting for all devices on the bus to go idle. When individual devices are idle, transactions on the bus are monitored and unclaimed transactions are claimed by the device clock controller, which then forces a retry of the transaction and reconnects the clock to the idle devices. This brings these devices from the low-power state to a full power state, where they are capable of claiming the transaction when it is retried.

Abstract: Video data (default data in case of a black original) output from a CCD line sensor 405 upon reading an image while a light source is kept OFF corresponds to beat noise contained in video data obtained upon reading an image while the light source is ON. After the beat noise data is stored, the correction data stored in a correction data storage unit is subtracted from video data read by a normal technique while the light source is ON in a correction memory, thus executing correction for removing beat noise. After the beat noise is removed in this way, when an image is formed under the control of a printer control unit, an image free from any beat noise can be obtained as an output image.

Abstract: When the user performs input seeking a message that pertains to the status of the device, the message display device of the present invention selects and displays based on the data generated by a data generator comprising a counter and/or a sensor an appropriate message from a group of messages, each of which corresponds to various input contents.

Abstract: Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device.

Abstract: A computer system is provided with a processor and a system board. The processor includes a processor core, at least one other non-processor core electronic component and a first non-volatile memory device. Stored inside the first non-volatile memory includes first programming instructions that provide initialization support for the at least one other non-processor core electronic component of the processor. The system board includes at least one non-processor electronic component and a second non-volatile memory device. Stored inside the second non-volatile memory device includes second programming instructions that provide initialization support for the at least one non-processor electronic component of the system board. Both the first and the second programming instructions further support a cooperative initialization protocol under which the first and second programming instructions cooperate with each other to initialize the computer system at power-on/reset.

Abstract: The present invention is a method and apparatus to provide functionalities to a system BIOS. The method comprises interfacing an interface module to the system BIOS, and receiving a request from the system BIOS to perform a task. System device information associated with the task is received from the system BIOS. The interface module translates the system device information to provide translated information. The translated information is then transferred to a corresponding module.

Abstract: Described is a clock circuit for supplying synchronized signals to a plurality of circuits. The clock circuit includes a clock generator and a driver for outputting the clock signals inputted from the clock generator with a delay time so that a difference among arrival times of the clock signals is minimized among the plurality of circuits.

Abstract: A system stream contiguous reproduction apparatus to which are input one or more system streams interleaving at least moving picture data and audio data, and system stream connection information includes a system clock STC generator for producing the system clock that is used as the system stream reproduction reference clock. The system stream contiguous reproduction apparatus further includes one or more signal processing decoders that operate referenced to the system clock STC, decoder buffers for temporarily storing the system stream data transferred to the corresponding signal processing decoders, and STC selectors for selecting a system clock STC referenced by the signal processing decoders when decoding the first system stream, and another system clock STC referenced by the signal processing decoders when decoding a second system stream reproduced contiguously to the first system stream.

Abstract: The present invention comprises a clocked bus keeper circuit that does not drive the bus during the first half of a clock cycle and then holds the value driven onto the bus during the first half of the clock cycle for the second half of the clock cycle. Accordingly, true data drivers on the bus drive the bus during the first half of the clock cycle without the need to overcome the value driven by the bus keeper, but during the second half of the clock cycle, the bus keeper holds the data driven during the first half of the clock cycle. In this manner, there is no bus contention between the true bus data drivers and the bus keeper.

Abstract: A computer-automated method of hierarchical event monitoring and analysis within an enterprise network including deploying network monitors in the enterprise network, detecting, by the network monitors, suspicious network activity based on analysis of network traffic data selected from the following categories: {network packet data transfer commands, network packet data transfer errors, network packet data volume, network connection requests, network connection denials, error codes included in a network packet}, generating, by the monitors, reports of the suspicious activity, and automatically receiving and integrating the reports of suspicious activity, by one or more hierarchical monitors.

Abstract: According to one embodiment, a computer system includes a Central Processing Unit (CPU), a hub agent and a hub interface coupled to the first hub agent. The computer system transitions from a first power state to a second power state upon the CPU determining that no requests are pending to access the first hub interface.

Abstract: A microprocessor with a variable clock operation, which is operative at a highest speed as well as a lowest speed, within a maximum performance range of the microprocessor is disclosed. The invention includes a microprocessor having a Critical Path Operation (CPO) block that is operative at a speed corresponding to an external clock signal; a decision circuit for deciding an operation state of the microprocessor, according to a test result of the CPO block in the microprocessor; a MUX unit for selecting a signal from either a signal from the decision circuit or an external signal, selecting a signal intended to control, and forwarding the selected signal; a controlling unit for receiving a signal from the MUX unit for providing a control signal for varying a clock signal; and a PLL circuit for varying the clock signal in response to the control signal from the controlling unit for applying a varied clock signal to the microprocessor.

Abstract: A computer system including a central processing unit and a system memory accessible to the central processing unit via a host bus. A primary non-volatile storage element and a backup non-volatile storage element are incorporated into the system's motherboard. The primary non-volatile storage element contains the system's boot code that is executed following a reset or power on event. The backup non-volatile storage element contains a restoration sequence that is suitable for reprogramming a first portion of the boot code in the primary non-volatile storage element. A jumper block on the motherboard determines which of the non-volatile storage elements is initially addressed following a power on event. Preferably, the first portion of the boot code comprises the system's boot block or gold code and includes a sequence for downloading and reprogramming remaining portions of the boot code. The primary non-volatile storage element is preferably implemented as a multiple sector flash memory device.

Abstract: One embodiment of the present invention provides a method for retrieving and installing device driver software across a network. The method operates by detecting the presence of a device in a computer system for which no current driver is installed in the computer system. Upon detecting such a device, the method reads a locator specifying the location of a current driver for the device from a non-volatile memory on the device. The method uses this locator to communicate with a remote host across the network, and to retrieve a current driver for the device from the remote host. Next, this current driver is installed on the computer system. In one embodiment of the present invention, the locator includes a universal resource locator (URL) and the network includes the Internet. One embodiment of the present invention reboots the computer system after installing the current driver.

Abstract: The present invention provides a method for centralized and managed loading of boot images into one or more processors that are part of a file server for a mass storage system. In a computer system having at least one first controller, at least one input output processor (IOP), a first bus and a second bus, the present invention includes the steps of detecting readiness of the IOP to load a boot image, identifying across the first bus a location where the boot image will be loaded and loading the boot image across the second bus. The first controller may determine which of a plurality of boot images should be loaded. The first controller and the IOP may each have first and second processors, with communication between the first processors being across the first bus and boot images being accessed by the second processors across the second bus.

Abstract: Each delay unit is divided into two delay unit groups, the preceding stage side and the succeeding stage side. To the delay unit group in the preceding stage side, power supply voltage is supplied via a power supply terminal, and to each delay unit of the delay unit group in the succeeding stage side, power supply voltage is supplied from the power supply terminal via a power supply control switch. A forward-pulse detecting circuit detects that forward pulse was propagated to a stage between the N-th stage and a stage a predetermined number of stages before the N-th, and outputs the detected result to the power supply control switch. With this operation, when forward pulse is propagated to the (N+1)th stage, power supply voltage is supplied also to the delay unit group in the succeeding stage side. As electric power is not supplied to the delay unit group in the succeeding stage side when forward pulse is not propagated to the (N+1)th stage, wasteful consumption of electric power is prevented.

Abstract: A control method and system for dynamically modulating the operation speed of a processor is disclosed. First, a current utility ratio of the processor is determined by an occurrence frequency of idle signals sent from a program executed on the processor. Next, control the processor to work at an operating clock in direct proportion to the current utility ratio. Therefore, the purposes of power conservation and temperature reduction can be achieved through appropriately lowering the operation speed when the utility ratio of the processor is lower.