Abstract: A method of network surveillance includes receiving network packets handled by a network entity and building at least one long-term and a least one short-term statistical profile from a measure of the network packets that monitors data transfers, errors, or network connections. A comparison of the statistical profiles is used to determine whether the difference between the statistical profiles indicates suspicious network activity.

Abstract: In complex systems, the arrival of data to a computation component is difficult to predict. A method of synchronizing the initiation of computation with the reception of its input data is disclosed. The method allows the input data and computation initiation commands to arrive in any order. The method is dynamically adjustable allowing for varying numbers of data inputs.

Abstract: A method for determining appropriate adjustments of computer system parameter values in order to improve system performance. The method for this determination is based on historical performance data. Methods are disclosed which involve measuring current system performance and retrieving paired stored values of measured system performance and a selected system parameter. The decision as to whether or not to adjust the value of the selected system parameter is based on performing a trend analysis on the paired values. When such changes are made, subsequent measurement of system performance is performed and beneficial changes are implemented.

Abstract: A circuit for aligning the phase of a parallel data signal to a clock signal. The circuit includes a parallel data terminal for receiving a parallel data signal formed by multiple word bits, a clock terminal for receiving a clock signal, and a data ready terminal for receiving a data ready signal which has a logic state transition aligned with a first information bit of the parallel data signal. A plurality of data signal delay and sampling circuits connected to the clock terminal and the parallel data terminal provide time-slice bit samples of each information bit of the parallel data signal. A comparator and decision circuit coupled to the clock terminal and at least one of the data signal delay and sampling circuits compares and selects one of the plurality of time-slice bit samples which is phase aligned with the clock signal.

Abstract: A method of managing alerts in a network including receiving alerts from network sensors, consolidating the alerts that are indicative of a common incident and generating output reflecting the consolidated alerts.

Abstract: A method of generating a configuration for a configurable spread spectrum communication device is disclosed herein. The method, implemented on a computing device having a processor and a computer readable memory, starts with a first step of receiving an input identifying a desired function, and a desired operation within the desired function, to be implemented by a configurable communication device. In a subsequent step, a signal flow path for the desired operation is generated by the computing device. Next, the desired operation is mapped onto a computing element within the configurable communication device; the computing element having localized control and being function-specific. The aforementioned steps are repeated to satisfy multiple operations required to enable the desired function.

Abstract: A portable computer includes a control for switching the configuration of the computer. An operator predefines one or more sets of computer configurations, and programmably assigns a configuration set to the control. The configuration change from a current configuration to a predefined configuration is made effective at any given time by activating the control. Exemplary controls include a key stroke, a hardware button, a software button (such as activated by a key combination or clicking device), a voice command, and an input from a wired or wireless remote device.

Abstract: Disclosed is a method for dynamically invoking power saving options in a battery powered device, such as a cellular telephone, so that the period of use or run-time of the device is extended. The user settable power saving options alter operation of the device in a way that reduces power consumption and extends run-time. The power saving options define the ways by which power is saved, such as less intensity for a backlight or slower scanning for a wireless accessory, and when they are invoked, based in part on a determination of the estimated or measured actual capacity in the battery. For example when a battery is at full capacity, all features may be fully operable and as the battery discharges some of the features may be disabled or work with reduced performance.

Abstract: A data collecting system is divided into first, second, and third information portions and includes at least one portable terminal for collecting data at a remote site. The terminal comprises a device for collecting data and a first memory for storing the first information portion. The terminal operates to sense the need for information for its use to generate an information call identifying the information and to respond to the information call for searching its memory for the information. If the information is available it is supplied for use by the portable terminal. The system further comprises a first mobile server which comprises a second memory for storing the second information portion, and responds to the information call for searching the second memory for the information. The system further includes a second server at a main information center. The second server comprises a third memory for storing the third information portion, and searches the third memory for the information.

Abstract: A power management system permits power-reduced operation of selected circuit blocks in a manner that requires no modification to other bus-coupled circuit blocks attempting to communicate with such selected circuit blocks. Consistent with one embodiment of the present invention, the approach is implemented in a digital electronic circuit arrangement having an accessing circuit block coupled to a clocked circuit block over a data bus. The clocked circuit block is power managed by decreasing, e.g., reducing or blocking, the clock speed to the clocked circuit block which impedes its ability communicate over the data bus. Once the clocked circuit block is set in a reduced power mode, the bus is monitored for data-access communications from the accessing circuit block to the clocked circuit block.

Abstract: A voltage sequencing circuit for applying a plurality of voltages to an electrical system in a predetermined sequence charges the input capacitance of a pass device to set the timing between successive power applications in the system. In one embodiment, a current source coupled to the gate terminal of a field effect transistor (FET) pass device is enabled when a previous voltage in the predetermined voltage sequence has achieved a desired level. The output current of the current source then begins to charge the gate terminal of the FET. When the gate voltage achieves a predetermined reference level, a drive unit applies a voltage to the gate terminal that exceeds a threshold voltage of the FET. The FET then causes the next voltage in the predetermined voltage sequence to be applied.

Abstract: A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.

Abstract: A method for deterministically booting a computer system having redundant components includes the step of selecting hardware and software components. The selected components are booted in a manner consistent with traditional computer systems. If the boot fails, a different set of components is selected and an attempt is made to boot those components traditionally. In one embodiment, the hardware and software components are a processor and an input/output controller. A corresponding apparatus is also discussed.

Abstract: A method and related computer system that allow monitoring at least one memory-accessing device, and adjusting pooling of data processing system memory devices in response to the monitoring.

Abstract: A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a destination register for retrieving the information. A first number of cycles before retrieval of the information to the destination register then is determined, and the information is transferred from the source register to delaying device, such as queuing device, for the first number of cycles. Finally, the information is written from the delaying device to the destination register. An apparatus for implementing variable length delay instructions includes an input line for reading information from a source register; delaying device for receiving said information read from the source register; a multiplexer; and a select line. A trigger signal is transmitted to the multiplexer, thereby instructing the multiplexer to write the information to a destination register.

Abstract: A method and apparatus are provided that configure a new network device via the network. The method consists of initiating a boot sequence on a first device. The boot process is suspended prior to performing network set up. The new device sends a configuration request to a computer on the network. The computer generates configuration data for the new device and sends configuration data the new device via a multicast message. The new device then writes the configuration data into a file used by an operating system for network configuration on the first device and continues the boot sequence.

Abstract: A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.

Abstract: An energy-saving control interface for power-on identification utilizes a first switch to start to sense and identify data. A second switch is connected to a sensing/scanning circuit for powering off the sensing/scanning circuit when a timer has reached its count. A third switch is used to control whether to supply power to a security control unit, wherein the security control unit is supplied with power immediately when the sensing/scanning circuit completes data identification. A power supply is connected with a fourth switch controlled by a confirmation signal from the security control unit, such that the security control unit determines whether to activate the power supply.

Abstract: A method, system, and program for network booting of a client computer is provided. The method comprises loading a special local bootstrap into a client computer and then using this special local bootstrap to save the client Interrupt Vector Table (IVT) to high memory and then passing control to a normal DOS bootstrap. From here a normal DOS boot is performed using files that contain pointers to the drivers of a network device which enables a specific network interface card. A special program is loaded which emulates a PXE application program interface and initiates a DHCP/PXE boot request to the network. In this manner, a client is able to perform a DHCP/PXE boot without specialized hardware, by relying on a software emulation of the necessary DHCP/PXE functions.

Abstract: An apparatus and method to provide a data processing system with reduced average power consumption while maintaining fast interrupt handling, and/or selectively change clock frequency for accessing memory with various access speeds. In a first embodiment, the invention provides a method to deterministically change a clock frequency between a first clock frequency and a second clock frequency in a data processing system to process operations upon the occurrence of a condition. In a second embodiment, the invention provides a method to change the clock frequency of a data processing system to process operations upon the occurrence of a condition. In a third embodiment, the invention provides a clock divider circuit to produce a core clock signal. In a fourth embodiment, the invention provides a data processing system with a deterministically variable processor clock.