Patents Examined by Thomas M. Heckler
  • Patent number: 6681332
    Abstract: A method for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: January 20, 2004
    Assignee: Analog Devices, Inc.
    Inventors: Michael Byrne, Nicola O'Byrne, Colin Price, Derek Hummerston
  • Patent number: 6675313
    Abstract: An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: January 6, 2004
    Assignee: Micron Technology, Inc.
    Inventor: David Cuthbert
  • Patent number: 6675312
    Abstract: A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. At least one of the plurality of signals may comprise an identical signal path while in the first mode and the second mode.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: January 6, 2004
    Assignee: Cypress Semiconductor Corp.
    Inventor: William G. Baker
  • Patent number: 6671816
    Abstract: A circuit for applying power to mixed mode integrated circuits in a predefined sequence. The circuit includes a first circuit powered by a first voltage and a second circuit powered by a second voltage that is less than the first voltage and having the second voltage coupled to the first circuit. The circuit for applying power to mixed mode integrated circuits includes a modified I/O cell of the second circuit. The modified I/O cell has a driver transistor including a back gate terminal, a gate terminal that is driven by the second circuit, a drain terminal that is coupled to a first circuit signal, and a source terminal that is coupled to the second voltage. The circuit for applying power to mixed mode integrated circuits further includes a controller circuit coupled to the first voltage and the second voltage supplied as controller circuit inputs. The controller circuit has a plurality of controller circuit outputs.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: December 30, 2003
    Assignee: Broadcom Corporation
    Inventor: Agnes N. Woo
  • Patent number: 6668332
    Abstract: Internal clock signals generated on a chip can be viewed externally by multiplexing the clock signals and functional output signals to pin that are used to view or access the functional output signals. JTAG facilities already provided on the chip are used to generate control signals that drive the multiplexers. By so doing no new input or output facilities are required to view the clock signals.
    Type: Grant
    Filed: February 15, 2000
    Date of Patent: December 23, 2003
    Assignee: International Business Machines Corporation
    Inventor: William Lloyd McNeil
  • Patent number: 6668334
    Abstract: A loss-of-clock (LOC) detector circuit detects a clock failure substantially within a specified number of clock periods and generates a loss-of-clock signal. The LOC detector includes a frequency-to-current converter which generates a charging current substantially proportional to a frequency of an input clock. A capacitor accepts the charging current and provides a terminal voltage that changes in response to the charging current. An edge detector receives the input clock signal as an input and produces an output pulse on an edge of the input clock signal. A switch is coupled to the capacitor such that the capacitor is discharged to a reference potential when the switch is closed. The switch is controlled by the edge detector to close when the edge detector output pulse is asserted. A comparator generates a loss-of-clock signal when the voltage on the capacitor passes a trip voltage of the comparator.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: December 23, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Christopher John Abel, Angelo Rocco Mastrocola, Douglas Edward Sherry, William Burdett Wilson
  • Patent number: 6668330
    Abstract: A method for providing a constant time reference to an operating system includes inputting a PCI clock and inputting a CPU clock. The method outputs a signal having a constant frequency which is a factor of the PCI clock and synchronized with the CPU clock. The method further involves using the output signal as the time reference for the operating system. The method provides a way by which the operating system can perform necessary tasks based on a constant time reference when the CPU clock is changing due to system power conservation requirements.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: December 23, 2003
    Assignee: Sun Microsystems, Inc.
    Inventor: Sanjiv Kapil
  • Patent number: 6665795
    Abstract: In one embodiment, a pipelined processor includes a reset unit that provides an output reset signal to at least one stage of the pipeline. The reset unit is adapted to detect at least a hard reset request, a soft reset request and an emulation reset request. The pipeline comprises N stages and the reset unit asserts the reset signal for at least N cycles of a clock after the reset request has been cleared. Each stage if the pipeline has a storage circuit for storing a corresponding valid bit. At least one of the storage circuits is cleared in response to the reset signal. In addition, the reset unit handles the reset request as a reset event having an assigned priority.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: December 16, 2003
    Assignees: Intel Corporation, Analog Devices, Inc.
    Inventors: Charles P. Roth, Ravi P. Singh, Gregory A. Overkamp
  • Patent number: 6662298
    Abstract: A system for execution of code while booting a computer system uses MMX registers of a processor as a virtual stack. BIOS instructions can cause the processor to execute a virtual stack push instruction to move a first data element from a general purpose register to a first MMX register. BIOS instructions can also execute a virtual stack pop instruction to move the first data element from the first of the MMX register to the general purpose register. The virtual stack push instruction and the virtual stack pop instruction are executable prior to initialization of a main memory.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: December 9, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Ed Heller
  • Patent number: 6662304
    Abstract: A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches in the packetized memory device. A clock generator circuit generates a plurality of internal clock signals responsive to the external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal. A plurality of selection circuits are coupled to the clock generator circuit and each has an output coupled to a clock terminal of an associated latch. Each selection circuit applies one of the internal clock signals to clock the associated latch in response to a phase command signal. An evaluation circuit receives digital signals sequentially stored in a selected one of the latches and generates a results signal indicating whether each of the digital signals has an expected value.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: December 9, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Brent Keeth, Terry R. Lee, Kevin Ryan, Troy A. Manning
  • Patent number: 6662301
    Abstract: A peripheral device which is connected with a host computer is prevented from unexpectedly coming to be in a disconnection state due to control of the host computer. Further, even when the peripheral device such as an electronic camera can not enough receive power necessary for the device itself from a connection line such as a USB, the peripheral device is made to be able to use the power effectively. To achieve the above, there is disclosed a computer peripheral device which is connected with the host computer and comprises a connection signal transmission unit for transmitting to the host computer a signal to control the connection with the host computer and a control unit for shifting an operation state of the computer peripheral device to a low consumption current mode after the connection signal transmission unit transmitted to the host computer a signal to control into the disconnection state.
    Type: Grant
    Filed: August 21, 2000
    Date of Patent: December 9, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masayoshi Sekine, Takashi Aizawa, Yuji Koide
  • Patent number: 6658563
    Abstract: A data processing system and method are described for booting a computer system from a virtual floppy diskette. A native operating system is executed by the computer system which utilizes a native file system. A boot able floppy diskette image is stored on the hard drive. The image includes a second operating system which utilizes a second file system. A master boot record stored on the hard drive is modified to include a boot bit. The boot bit is set in response to a storage of the image. The computer system is then booted from the image in response to the boot bit being set. The native operating system and the native file system are unchanged during the booting of the computer system from the image.
    Type: Grant
    Filed: May 18, 2000
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Herbert Jackson Ice, Jr., Robert Duane Johnson, Kofi Kekessie, David Rhoades, Gary Anthony Vaiskauckas
  • Patent number: 6654937
    Abstract: A method and apparatus is provided for enabling a static timing tool to analyze and test register files in integrated circuits to find correct paths and ignore detected contention. This is achieved by utilizing pattern matching in the static timing tool and having the tool perform certain operations on the transistors of the pattern matched. The methodology includes considering the write word lines as clock nodes, disabling signal propagation through the memory element components, forcing predetermined internal nodes to be of inverse polarity, establishing signal direction through the circuit elements, and indicating that one or more of the predetermined nodes are not to be reported.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: November 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Matthew J. Amatangelo, Christopher McCall Durham, Peter Juergen Klim
  • Patent number: 6651165
    Abstract: A computer system operating system (OS) is booted from a storage media formed from a redundant array of independent disks (RAID). An interface adapter is connected to a system bus, and the interface adapter includes a nonvolatile option ROM memory which has RAID I/O algorithmic instructions recorded therein. When a basic input output system (BIOS) is executed during booting, a BIOS hardware detect instruction set of the BIOS scans the system bus and causes the RAID I/O algorithmic instructions to be read from the option ROM memory for use by a BIOS I/O instruction set, and the BIOS I/O instruction set uses the RAID I/O algorithmic instructions obtained from the option ROM memory to read the OS from the RAID storage media.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: November 18, 2003
    Assignee: LSI Logic Corporation
    Inventor: Harold L. Johnson
  • Patent number: 6647492
    Abstract: A method and apparatus for achieving the appearance of persistent memory in a system environment requiring persistent memory using a device having non-persistent memory. More particularly, the device having non-persistent memory has volatile memory and a storage device.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: November 11, 2003
    Assignee: NCR Corporation
    Inventors: Robert H. Nathan, Alan F. Hartman
  • Patent number: 6647501
    Abstract: A power supply controller measures electrical power consumed by information processing apparatus. An embedded controller passes the data to power management utility software each time a specified length of time is elapsed. The utility software accumulates a difference as found between this consumed power level and a predetermined reference value. The utility software shifts the information processing apparatus into its power-save modes when the accumulated value becomes larger than the predetermined value.
    Type: Grant
    Filed: April 18, 2000
    Date of Patent: November 11, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryoji Ninomiya
  • Patent number: 6643785
    Abstract: A CPU deactivates an A/D converter section before it stops operating in an idle mode. When any one of the keys in key matrices is pushed, the key matrix including the key pushed generates a voltage. The voltage is applied to the A/D converter section and one of buffer circuits. If the voltage is lower than the threshold voltage of the buffer circuit, the output signal of an AND circuit changes, and an interrupt-signal generating circuit generates a signal for releasing the idle mode. In response to this signal, the CPU starts operating and activates the A/D converter section.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: November 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiyuki Kamimura, Koichi Teraya
  • Patent number: 6643792
    Abstract: Multi-processor system including processors, a host-PCI bridge, and other devices which are connected to each other by a processor bus and a clock control bus for clock frequency adjustment. Each of the processors, a host-PCI bridge, and other devices operate in synchronism with others based on clocks generated by incorporated clock generation circuits. Each of the processors, a host-PCI bridge, and other devices dynamically execute clock frequency changing operations to the incorporated clock generation circuits by using at least the clock control bus in synchronism with others. Thus, the frequencies of clocks generated by each of the processors, a host-PCI bridge, and other devices can be dynamically changed in synchronism with others.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: November 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiko Kurosawa
  • Patent number: 6640311
    Abstract: A circuit includes a signal generator and a discriminator. The signal generator generates a plurality of reference signals where a majority of the reference signals have the same phase. The discriminator generates a regulated signal that has the same phase as the majority of the reference signals. Therefore, if an environmental disturbance such as a single-event transient (SET) shifts the phase or phases of a minority of the reference signals, the discriminator maintains the regulated signal at a stable frequency and phase by generating the regulated signal with reference to the undisturbed majority of the reference signals.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: October 28, 2003
    Assignee: BAE Systems Information and Electronic Systems Integration, Inc.
    Inventor: Kenneth R. Knowles
  • Patent number: 6636976
    Abstract: The present invention provides a mechanism for adjusting the activity of an integrated digital circuit such as a processor to reduce voltage changes attributable to current changes triggered by clock gating. The processor includes one or more functional units and a current control circuit that monitors activity states of the processor's functional units to estimate the current consumed over n clock cycles. The current control circuit estimates the current change for a given clock cycle from the n activity states and compares the estimated current change with first and second thresholds. The processors activity is decreased if the estimated current change is greater than the first threshold, and the processor activity is decreased if the estimated current change is less than the second threshold.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: October 21, 2003
    Assignee: Intel Corporation
    Inventors: Edward T. Grochowski, David Sager, Vivek Tiwari, Ian Young, David J. Ayers