Abstract: A SCSI initiator, repeater, or device is provided that stretches an initial assertion of the REQ# or ACK# clock signals on the SCSI bus after a period of inactivity on the SCSI data lines. This discharges built up charge allowing greater signal integrity on ensuing clocks.

Abstract: A method which permits self-synchronization of elements to be synchronized. Synchronization is neither implemented nor managed by a central entity. By shifting synchronization into each element, more synchronization tasks can also be performed simultaneously, because independent elements no longer interfere with one another when accessing the central synchronization entity. In a module with a two- or multi-dimensionally arranged programmable cell structure, each configurable element can access the configuration and status register of other configurable elements over an interconnecting structure and thus can have an active influence on their function and operation. The configuration can thus be accomplished by a load logic from a processing array.

Abstract: A method of updating the system time of a data processor system that stores the actual system time which is linked to a subscriber station and a communication service of a communications network. The subscriber station of the data processor system communicates a message that contains the subscriber station's own address as the destination address. Upon receipt of this message, the time-related information of the message is parsed and transferred into a memory of the data processor system.

Abstract: A method for synchronizing a slave system and a master system, the method including the steps of providing a slave clock signal based on a communicated master clock signal, providing a time frame in the slave system, wherein the time frame is defined by a minimum time and a maximum time, and a phase of the slave clock signal corresponds to an actual time, determining if the slave clock signal is in the time frame, and regulating the slave clock signal, if it is not in the time frame, so that the slave clock signal occurs within the time frame.

Abstract: A programmer system and method of programming programmable micro devices with significantly increased throughput are provided. The programmer system includes a multiple number of sockets for programming a multiple number of micro devices simultaneously. A buffer circuit is also provided which is capable of providing a number of logic levels suitable to drive different micro devices during programming by a programmer system adapted to program a number of micro devices simultaneously. A method for programming a programmable micro device is further provided which uses the standard bus cycle from a processor for programming. Finally, a data compare circuit and a method for verifying data programmed by a programmer in a plurality of programmed micro devices using a single read-back operation is also disclosed.

Abstract: A method and system to verify the passage of one or more write commands sent from an originating location through a PCI bus system. An addressable data storage is located substantially at the end of the PCI bus system with respect to the originating location. A write command is sent by the originator subsequent to the one or more write commands, to a predetermined special end location address identifying the addressable storage. The command is accompanied by data comprising a predetermined special return address at the originating location. The PCI bus system transmits the write commands on a FIFO basis, so the one or more write commands precede the subsequently sent write command. Logic senses the subsequently sent write command, and responds to the command, sending a return echo write command to the predetermined special return address. The returning echo write command verifies the passage of the write commands and data through the PCI bus system.

Abstract: A method and system for running, on different computers at the same time, multiple operating systems from the same shared system resource is provided. This is accomplished, for example, by using persistent elemental disk reservations. Each machine reads the master boot record without reservation to determine the partition of the operating system to be booted. Each machine then makes an elemental exclusive write persistent reservation for accessing the operating system boot partition. This is followed by each machine making another elemental exclusive write persistent reservation for accessing the operating system partition itself. Each machine is assigned a different operating system partition even if they are running the same operating system. The unique reservation key for these reservations is created from at least on of a Processor ID, a Cluster ID, a Multiple Processor partition ID, a Non-Uniform Memory Access complex ID, and/or a Non-Uniform Memory Access node ID.

Abstract: One embodiment of the present invention provides a system that retrieves and installs device driver software across a network. The system includes a detection mechanism that detects the presence of a device in a computer system for which no current driver is installed in the computer system. The system also includes a reading mechanism that reads a locator specifying the location of a current driver for the device from a non-volatile memory on the device. The system additionally includes a driver retrieving mechanism that uses the locator to communicate with a remote host across the network in order to retrieve the current driver for the device from the remote host. The system also includes an installation mechanism that installs the current driver on the computer system.

Abstract: A system for reducing the startup current demand of a computer system by providing clock signals at normal operating frequencies to a plurality of computer components in a staggered progression. The computer system includes a clock buffer having a plurality of outputs each for providing a clock signal to at least one computer component. During the startup of the computer system, the clock buffer provides at each output a clock signal at a normal operating frequency to each component in a staggered progression with the other outputs. Consequently, only one component (or component group) becomes operational at a time during the startup of the computer system. In one example, each output of the clock buffer is coupled to a memory module that includes multiple SDRAM chips.

Abstract: An apparatus and method are described for reducing the timing skew on a printed circuit board including a plurality of conductive traces interconnecting a first node and a second node. At least one section is removed from at least one printed circuit board trace to thereby sever a trace and prevent signals passing from the first node to the second node from following the severed trace. In this manner, signal path length can be adjusted to reduce timing skews in the circuit. Sections are removed from the traces by using a laser, CVD, a router, a plasma or by passing sufficient current through weakened areas of the traces.

Abstract: A method and system for referring to and binding to objects using a moniker object is provided. In a preferred embodiments moniker object contains information to identify linked source data and provides methods through which a program can bind to the linked source data. A binding method is provided that returns an instance of an interface through which the linked source data can be accessed. The moniker object can identify source data that is stored persistently or nonpersistently. In addition, moniker objects can be composed to form a composite moniker object. A composite moniker object is used to identify linked source data that is nested in other data. In a preferred embodiment, the moniker object provides other methods including a reducing method that returns a more efficient representation of the moniker object; equality and hash methods for comparing moniker objects; and inverse, common prefix, and relative-path-to methods for comparing and locating moniker objects from other moniker objects.

Abstract: A system for execution of code during power-on-self test (POST), the system including a mass storage device for storing computer programs; a microprocessor connected to the mass storage device, the microprocessor including an execution unit; a general purpose register connected to the execution unit, the general purpose register for storing a first data element; an MMX unit including a plurality of MMX registers, the MMX unit connected to the general purpose register, wherein the plurality of MMX registers are configurable as a virtual stack; a storage device connected to the microprocessor, the storage device for storing BIOS instructions; and a plurality of BIOS instructions stored on the storage device, the plurality of BIOS instructions readable by the microprocessor to thereby cause the microprocessor to execute a virtual stack push instruction wherein the first data element is moved from the general purpose register to a first of the plurality of MMX registers; and execute a virtual stack pop instructio

Abstract: Provided is a method and components of an apparatus for implementing a method for assisting with adjustment of the timing of user-inactivity-dependent changes of operational state of an apparatus, by identifying user interactions following a change of operational state, determining when the user's interactions or lack of interaction following the change of state suggest that a change to an inactivity time period is desirable, and either automatically changing the inactivity time period or prompting the user to change the time period.

Abstract: Methods and system for providing selectable initialization sequences are disclosed. The method of initializing a system includes providing at least one reference associated with a device coupled to the system. A user selects the reference associated with the device and an initialization sequence is determined based upon the selected reference.

Abstract: A method for recovering a clock signal communicated on a system bus. The method includes receiving at a receiver a first signal having a first polarity and receiving at the receiver a second signal having an opposite polarity to the first signal. The method also includes generating at the receiver a first clock signal based upon the first signal and the second signal.

Abstract: A clock and data separator circuit and method that separates data and clock signals that may coincide. The separator circuits use CMOS transistors to extend the time separation between transitions in the data signals and transitions in clock signals. The processing circuitry comprises pass gates that are selectively controlled to delay the latter of the input signals received at substantially the same time. In one embodiment the processing circuitry, or separator circuit, comprises a signal separator circuit that has two controllable current paths. In such an embodiment, whichever signal arrives first in time will delay the transition of the second arriving signal. In another embodiment, the processing circuitry comprises pass transistors that control a propagation path of a first input signal. The pass transistors are controlled by a second input signal. Likewise, whichever signal arrives first in time will delay the transition of the second arriving signal.

Abstract: A method and apparatus for protecting smart cards against simple and differential power attacks when they are inserted into card readers controlled by other entities. The technique is particularly useful in financial applications such as ATM cards, credit cards, and electronic wallets, in which cards have to be inserted into card readers which may be specifically manufactured or modified to perform undetectable measurements of the power supplied to the card during its normal operation. The basic technique is to use two capacitors embedded in the smart card in such a way that at any given time one of them is charged by the external power supply and the other one is discharged by powering the smart card chip. The roles of the two capacitors alternate rapidly, and the power supply is detached from the smart card chip in the sense that external power measurements do not reveal information about its internal operations.

Abstract: A system stream contiguous reproduction apparatus to which are input one or more system streams interleaving at least moving picture data and audio data, and system stream connection information includes a system clock STC generator for producing the system clock that is used as the system stream reproduction reference clock. The system stream contiguous reproduction apparatus further includes one or more signal processing decoders that operate referenced to the system clock STC, decoder buffers for temporarily storing the system stream data transferred to the corresponding signal processing decoders, and STC selectors for selecting a system clock STC referenced by the signal processing decoders when decoding the first system stream, and another system clock STC referenced by the signal processing decoders when decoding a second system stream reproduced contiguously to the first system stream.

Abstract: A system stream contiguous reproduction apparatus to which are input one or more system streams interleaving at least moving picture data and audio data, and system stream connection information includes a system clock STC generator for producing the system clock that is used as the system stream reproduction reference clock. The system stream contiguous reproduction apparatus further includes one or more signal processing decoders that operate referenced to the system clock STC, decoder buffers for temporarily storing the system stream data transferred to the corresponding signal processing decoders, and STC selectors for selecting a system clock STC referenced by the signal processing decoders when decoding the first system stream, and another system clock STC referenced by the signal processing decoders when decoding a second system stream reproduced contiguously to the first system stream.

Abstract: In a multi-node non-uniform memory access (NUMA) multi-processor system, a designated node synchronization processor on each node, is synchronized. Individual nodes accomplish internal synchronization of the other processors on each node utilizing well known techniques. Thus it is sufficient to synchronize one processor on each node. Node zero, a designated system node that acts as a synchronization manager, estimates the time it takes to transmit information in packet form to a particular, remote node in the system. As a result a time value is transmitted from the remote node to node zero. Node zero projects the current time on the remote node, based on the transmission time estimate and compares that with its own time and either updates its own clock to catch up with a leading remote node or sends a new time value to the other node, requiring the remote node to advance its time to catch up with that on node zero.